From patchwork Thu May 18 18:45:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jisheng Zhang X-Patchwork-Id: 13247262 X-Patchwork-Delegate: mail@conchuod.ie Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 71A68C7EE23 for ; Thu, 18 May 2023 18:57:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=m46+R1mgrrqrk+hJwdIXy9BS8gmbrp3BdMd+hlQKF1Y=; b=10Nfr9UrPYccLi OO2Sfwe6B0EInKFmswSlVtRcqIWyFrfrQRuzn8RvXhl/SRZEcKfoUmSaZC2DSiDJbPtH7CUD27hEU eotrko1PtaMD6Xger6gJNgm8Qej2LX/gkjAXWuj8rtxuHr3Fv82JcU6zv5ZTUsuRAMK0miqLmczj+ KwppojahigTu3lNpNKOlE9Gl3sbQvmgt16dudTl9FIzKzOqBdYiJ1B4K7zW8s2Ru5/+9vC3YJAhvi DNg+6R+fh5rS5OCUPB4A3KesdvwZDS8ks/Wscpr8BQa6mGhTSOZoapfyGr29/rI6q7HjKf/ubY1Ju WO0P3mI0N1xDhbwaO31g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1pzioJ-00Dsz0-1r; Thu, 18 May 2023 18:57:11 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1pzioH-00Dsxv-14 for linux-riscv@lists.infradead.org; Thu, 18 May 2023 18:57:10 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id D924D651BF; Thu, 18 May 2023 18:57:08 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 03542C4331E; Thu, 18 May 2023 18:57:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1684436227; bh=Hxt77XTd4sJ4iSsW4a+tGjggeRmSDhhjr46ffLnz1is=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ozM0GDlhAZV8HvMUYO9tXWmKQKFJ9BVbHZS3eBKkSx/LEFwoXPchpJCjWLpb4zp5K exANsNP2OcsiyOaErwuldCtwi97q3hKqXFUXC5e9rXiiX/u5WFwp9KD2rc0tTv6eWP o9GzOQYbCiH2x4EGtMDkWy0hd1hUMHiI9bDqfGu2E5w9njF9Q90a+FpJED1rUXLWGx ICt8X8CP4RQxC00MmpdH/7bWShTEqX2d9XcEJJ2zo267E7fJgybAKWTsLKNhcmyEXq RFPVyuLF7YlNMHb7rB7hjWivqCR5d/pMnh9ES2G0fMqXPQw9ikRg9PzpGwWVklQwak jh/dLVW4bHlug== From: Jisheng Zhang To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou , Guo Ren Subject: [PATCH v2 5/9] riscv: Add the T-HEAD SoC family Kconfig option Date: Fri, 19 May 2023 02:45:37 +0800 Message-Id: <20230518184541.2627-6-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230518184541.2627-1-jszhang@kernel.org> References: <20230518184541.2627-1-jszhang@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230518_115709_417688_EBD3B9D7 X-CRM114-Status: GOOD ( 10.18 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Yangtao Li , linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Wei Fu Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The first SoC in the T-HEAD series is TH1520, containing quad T-HEAD C910 cores. Signed-off-by: Jisheng Zhang Reviewed-by: Conor Dooley --- arch/riscv/Kconfig.socs | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 1cf69f958f10..ce10a38dff37 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -41,6 +41,12 @@ config ARCH_SUNXI This enables support for Allwinner sun20i platform hardware, including boards based on the D1 and D1s SoCs. +config ARCH_THEAD + bool "T-HEAD RISC-V SoCs" + select ERRATA_THEAD + help + This enables support for the RISC-V based T-HEAD SoCs. + config ARCH_VIRT def_bool SOC_VIRT