| Message ID | 20230529121503.3544-2-changhuang.liang@starfivetech.com (mailing list archive) |
|---|---|
| State | Handled Elsewhere |
| Headers | show |
| Series | Add JH7110 MIPI DPHY RX support | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/tree_selection | fail | Failed to apply to next/pending-fixes, riscv/for-next or riscv/master |
Hey Changhuang, Couple of minor bits from me here, you don't need to fix them unless the binding has to change for other reasons. On Mon, May 29, 2023 at 05:15:01AM -0700, Changhuang Liang wrote: > StarFive SoCs like the jh7110 use a MIPI D-PHY RX controller based on > a M31 IP. Add a binding for it. > > Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com> > --- > .../bindings/phy/starfive,jh7110-dphy-rx.yaml | 71 +++++++++++++++++++ > 1 file changed, 71 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-rx.yaml > > diff --git a/Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-rx.yaml b/Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-rx.yaml > new file mode 100644 > index 000000000000..46fd370188e8 > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-rx.yaml > @@ -0,0 +1,71 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/starfive,jh7110-dphy-rx.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: StarFive SoC MIPI D-PHY Rx Controller nit: either s/SoC/JH7110/ or s/SoC//. > + > +maintainers: > + - Jack Zhu <jack.zhu@starfivetech.com> > + - Changhuang Liang <changhuang.liang@starfivetech.com> > + > +description: > + The StarFive SoC uses the MIPI CSI D-PHY based on M31 IP to transfer > + CSI camera data. nit: "Starfive SoCs contain a MIPI CSI D-PHY based on an M31 IP, used to transfer CSI camera data." > +properties: > + compatible: > + const: starfive,jh7110-dphy-rx > + > + reg: > + maxItems: 1 > + > + clocks: > + items: > + - description: config clock > + - description: reference clock > + - description: escape mode transmit clock > + > + clock-names: > + items: > + - const: cfg > + - const: ref > + - const: tx > + > + resets: > + items: > + - description: DPHY_HW reset > + - description: DPHY_B09_ALWAYS_ON reset I'd prefer not to have what looks like copy-paste from a datasheet and instead a description of what they do. Otherwise, this looks grand to me, but I don't understand the hardware so there is no point in me leaving an R-b on this. Hopefully Krzysztof can take a look at it in the coming days. Thanks, Conor.
On 2023/5/29 22:05, Conor Dooley wrote: > Hey Changhuang, > > Couple of minor bits from me here, you don't need to fix them unless > the binding has to change for other reasons. > Thanks for your comments. [...] >> +$id: http://devicetree.org/schemas/phy/starfive,jh7110-dphy-rx.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: StarFive SoC MIPI D-PHY Rx Controller > > nit: either s/SoC/JH7110/ or s/SoC//. > Changed to "StarFive JH7110 SoC MIPI D-PHY Rx Controller"? >> + >> +maintainers: >> + - Jack Zhu <jack.zhu@starfivetech.com> >> + - Changhuang Liang <changhuang.liang@starfivetech.com> >> + >> +description: >> + The StarFive SoC uses the MIPI CSI D-PHY based on M31 IP to transfer >> + CSI camera data. > > nit: "Starfive SoCs contain a MIPI CSI D-PHY based on an M31 IP, used to > transfer CSI camera data." > Will fixed this. >> +properties: >> + compatible: >> + const: starfive,jh7110-dphy-rx [...] >> + resets: >> + items: >> + - description: DPHY_HW reset >> + - description: DPHY_B09_ALWAYS_ON reset > > I'd prefer not to have what looks like copy-paste from a datasheet > and instead a description of what they do. > > Otherwise, this looks grand to me, but I don't understand the hardware > so there is no point in me leaving an R-b on this. > Hopefully Krzysztof can take a look at it in the coming days. > I will wait for Krzysztof's comments.
On Mon, 29 May 2023 05:15:01 -0700, Changhuang Liang wrote: > StarFive SoCs like the jh7110 use a MIPI D-PHY RX controller based on > a M31 IP. Add a binding for it. > > Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com> > --- > .../bindings/phy/starfive,jh7110-dphy-rx.yaml | 71 +++++++++++++++++++ > 1 file changed, 71 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-rx.yaml > Reviewed-by: Rob Herring <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-rx.yaml b/Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-rx.yaml new file mode 100644 index 000000000000..46fd370188e8 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-rx.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/starfive,jh7110-dphy-rx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive SoC MIPI D-PHY Rx Controller + +maintainers: + - Jack Zhu <jack.zhu@starfivetech.com> + - Changhuang Liang <changhuang.liang@starfivetech.com> + +description: + The StarFive SoC uses the MIPI CSI D-PHY based on M31 IP to transfer + CSI camera data. + +properties: + compatible: + const: starfive,jh7110-dphy-rx + + reg: + maxItems: 1 + + clocks: + items: + - description: config clock + - description: reference clock + - description: escape mode transmit clock + + clock-names: + items: + - const: cfg + - const: ref + - const: tx + + resets: + items: + - description: DPHY_HW reset + - description: DPHY_B09_ALWAYS_ON reset + + power-domains: + maxItems: 1 + + "#phy-cells": + const: 0 + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - power-domains + - "#phy-cells" + +additionalProperties: false + +examples: + - | + phy@19820000 { + compatible = "starfive,jh7110-dphy-rx"; + reg = <0x19820000 0x10000>; + clocks = <&ispcrg 3>, + <&ispcrg 4>, + <&ispcrg 5>; + clock-names = "cfg", "ref", "tx"; + resets = <&ispcrg 2>, + <&ispcrg 3>; + power-domains = <&dphy_pwrc 1>; + #phy-cells = <0>; + };
StarFive SoCs like the jh7110 use a MIPI D-PHY RX controller based on a M31 IP. Add a binding for it. Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com> --- .../bindings/phy/starfive,jh7110-dphy-rx.yaml | 71 +++++++++++++++++++ 1 file changed, 71 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-rx.yaml