From patchwork Wed Jun 14 10:47:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prabhakar X-Patchwork-Id: 13279906 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 83CA2C001DD for ; Wed, 14 Jun 2023 10:48:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=ozey3Sy/CgRvY/HJOc1vBX2QA56PHoV0mIIqO23/F2k=; b=gn/fdVl3DAHYv/ PUkDzqWnueASC27VG38PMUdA2iE8nHDM8ZYCgn8F39mJCnZ89O/A5BiEGrB2dtW3nQr0Oyen2A4OI rcgHhbeo8nufFewELk046QoHKfYyscY/yPbtZxz0GOtJx+/faVkpTOtYYepo8SReIP9VblR4/+vda 7++0ZqcL1FcFcyPL3ScHr3SJYo3X1/SNmFUXVeHpJcuwNXzZiyfCoHrukeJVcR5m3s/l/6d9SFy3g 72YHegBTsgjhchrJueDASEVzMpKRd6u40Gdmw48P9Aws4L39tnqiL4GYSkvGZalwYM08HxXYYOt8G DgCAwZttcFAAmuYuMq6g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1q9O2z-00BHDx-1q; Wed, 14 Jun 2023 10:48:17 +0000 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1q9O2s-00BH4c-05 for linux-riscv@lists.infradead.org; Wed, 14 Jun 2023 10:48:11 +0000 Received: by mail-wm1-x32c.google.com with SMTP id 5b1f17b1804b1-3f8cdb12719so4153915e9.1 for ; Wed, 14 Jun 2023 03:48:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1686739688; x=1689331688; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=54awEcwIqAI+xJ9eKb8uhlwdu40FnMLdikz9jtZBxm4=; b=dOf21LQJi4YaxOaXsTRIRBfl5mzMPsK/ljTLaVc7Sf/IEKb5nPBBzLkza5lqDVjJlk gswK/LmWfmJCguDWOYIzkNz8la2pIfITbbdGdHcqgF3H8GfexMsTOYPxnCLRvnrl6zFy gB3ocwnBQlR/ZvuksBy3f14zo5ru+bh26cHxXLrVO2MegCYUozMHeEhM2cRzau/gAFMP 9cqC4D6Am/thiWBJmlgMQXgaiAW1USkE9UNdAabcgGN2OhSO+jcaAcJGky8Rb66BgHIe WNzUCvoSljptc7+esj381mZ0gBu6E/EZZBY1RXqQ9JScvy5JM1NuaOo0yCUw21w3+UkW rwQA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686739688; x=1689331688; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=54awEcwIqAI+xJ9eKb8uhlwdu40FnMLdikz9jtZBxm4=; b=ZckRhvMYZ173KfSnFFPFfJrimjlhz2MLt2nA69nmkVfXp4rWZylS6//lHIlNsPB/q/ TOt96EEf7+Upyy0CpfZXOkp9ytsTixJKY4sptu2jnCjbegi9nam5XqbvwfAmKgJYRYfA 8FR3b5PQa7klG93AEpfWx47SKSr1WBAc6lvnpa2Czpqx6zYoDymSdQ5SbAJ2LeO5ff6z UtzBqpxxcLu20sbRSBt9Je8tG+UEezSWuYr6OqCYFjIMJQhsDBQsYkyOapkFitj+aabQ iM5JqNVGWWOSesJnCPQmp5oGVCOeGXBCOfm3Gj1SaK7vlTa5xwh5EfpN/bE2I4UmOcQF MTgg== X-Gm-Message-State: AC+VfDzQlbc1qZOcxVCPUTnvnxq3/1yFXZjIub6MdOPPaRvn8pCaM92f MjlZlV34nv1fi8CRzA1yZkw= X-Google-Smtp-Source: ACHHUZ5P4TrP2GYMKWeWTFq+27scIGpqfV0wL9ukpLCckZxd7nluyFYMvOYPe90VCMfY4x9iqhxueA== X-Received: by 2002:a7b:cb92:0:b0:3f5:ffe3:46a7 with SMTP id m18-20020a7bcb92000000b003f5ffe346a7mr9503412wmi.9.1686739687813; Wed, 14 Jun 2023 03:48:07 -0700 (PDT) Received: from prasmi.home ([2a00:23c8:2501:c701:64d6:8737:b80d:a298]) by smtp.gmail.com with ESMTPSA id y10-20020a1c4b0a000000b003f5ffba9ae1sm17154904wma.24.2023.06.14.03.48.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Jun 2023 03:48:07 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Arnd Bergmann , Conor Dooley , Geert Uytterhoeven , Guo Ren , Andrew Jones , Paul Walmsley , Palmer Dabbelt , Albert Ou , Samuel Holland , linux-riscv@lists.infradead.org, Christoph Hellwig Cc: Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar , Biju Das , Lad Prabhakar Subject: [PATCH v9 3/6] riscv: mm: dma-noncoherent: nonstandard cache operations support Date: Wed, 14 Jun 2023 11:47:56 +0100 Message-Id: <20230614104759.228372-4-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230614104759.228372-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20230614104759.228372-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230614_034810_077952_F0C340B6 X-CRM114-Status: GOOD ( 19.76 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Lad Prabhakar Introduce support for nonstandard noncoherent systems in the RISC-V architecture. It enables function pointer support to handle cache management in such systems. This patch adds a new configuration option called "RISCV_NONSTANDARD_CACHE_OPS." This option is a boolean flag that depends on "RISCV_DMA_NONCOHERENT" and enables the function pointer support for cache management in nonstandard noncoherent systems. Signed-off-by: Lad Prabhakar Reviewed-by: Conor Dooley --- v8 -> v9 * New patch --- arch/riscv/Kconfig | 7 ++++ arch/riscv/include/asm/dma-noncoherent.h | 28 +++++++++++++++ arch/riscv/mm/dma-noncoherent.c | 43 ++++++++++++++++++++++++ arch/riscv/mm/pmem.c | 13 +++++++ 4 files changed, 91 insertions(+) create mode 100644 arch/riscv/include/asm/dma-noncoherent.h diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 628aad4fb6e2..325ab2124f0a 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -261,6 +261,13 @@ config RISCV_DMA_NONCOHERENT select ARCH_HAS_SYNC_DMA_FOR_DEVICE select DMA_DIRECT_REMAP +config RISCV_NONSTANDARD_CACHE_OPS + bool + depends on RISCV_DMA_NONCOHERENT + help + This enables function pointer support for non-standard noncoherent + systems to handle cache management. + config AS_HAS_INSN def_bool $(as-instr,.insn r 51$(comma) 0$(comma) 0$(comma) t0$(comma) t0$(comma) zero) diff --git a/arch/riscv/include/asm/dma-noncoherent.h b/arch/riscv/include/asm/dma-noncoherent.h new file mode 100644 index 000000000000..f4e9bb2d3800 --- /dev/null +++ b/arch/riscv/include/asm/dma-noncoherent.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2023 Renesas Electronics Corp. + */ + +#ifndef __ASM_DMA_NONCOHERENT_H +#define __ASM_DMA_NONCOHERENT_H + +#include + +/* + * struct riscv_cache_ops - Structure for CMO function pointers + * + * @clean: Function pointer for clean cache + * @inval: Function pointer for invalidate cache + * @flush: Function pointer for flushing the cache + */ +struct riscv_cache_ops { + void (*clean)(phys_addr_t paddr, unsigned long size); + void (*inval)(phys_addr_t paddr, unsigned long size); + void (*flush)(phys_addr_t paddr, unsigned long size); +}; + +extern struct riscv_cache_ops noncoherent_cache_ops; + +void riscv_noncoherent_register_cache_ops(const struct riscv_cache_ops *ops); + +#endif /* __ASM_DMA_NONCOHERENT_H */ diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoherent.c index b9a9f57e02be..4cdaa879839a 100644 --- a/arch/riscv/mm/dma-noncoherent.c +++ b/arch/riscv/mm/dma-noncoherent.c @@ -9,13 +9,26 @@ #include #include #include +#include static bool noncoherent_supported; +struct riscv_cache_ops noncoherent_cache_ops = { + .clean = NULL, + .inval = NULL, + .flush = NULL, +}; + static inline void arch_dma_cache_wback(phys_addr_t paddr, size_t size) { void *vaddr = phys_to_virt(paddr); +#ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS + if (unlikely(noncoherent_cache_ops.clean)) { + noncoherent_cache_ops.clean(paddr, size); + return; + } +#endif ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size); } @@ -23,6 +36,13 @@ static inline void arch_dma_cache_inv(phys_addr_t paddr, size_t size) { void *vaddr = phys_to_virt(paddr); +#ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS + if (unlikely(noncoherent_cache_ops.inval)) { + noncoherent_cache_ops.inval(paddr, size); + return; + } +#endif + ALT_CMO_OP(inval, vaddr, size, riscv_cbom_block_size); } @@ -30,6 +50,13 @@ static inline void arch_dma_cache_wback_inv(phys_addr_t paddr, size_t size) { void *vaddr = phys_to_virt(paddr); +#ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS + if (unlikely(noncoherent_cache_ops.flush)) { + noncoherent_cache_ops.flush(paddr, size); + return; + } +#endif + ALT_CMO_OP(flush, vaddr, size, riscv_cbom_block_size); } @@ -50,6 +77,13 @@ void arch_dma_prep_coherent(struct page *page, size_t size) { void *flush_addr = page_address(page); +#ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS + if (unlikely(noncoherent_cache_ops.flush)) { + noncoherent_cache_ops.flush(page_to_phys(page), size); + return; + } +#endif + ALT_CMO_OP(flush, flush_addr, size, riscv_cbom_block_size); } @@ -75,3 +109,12 @@ void riscv_noncoherent_supported(void) "Non-coherent DMA support enabled without a block size\n"); noncoherent_supported = true; } + +void riscv_noncoherent_register_cache_ops(const struct riscv_cache_ops *ops) +{ + if (!ops) + return; + + noncoherent_cache_ops = *ops; +} +EXPORT_SYMBOL_GPL(riscv_noncoherent_register_cache_ops); diff --git a/arch/riscv/mm/pmem.c b/arch/riscv/mm/pmem.c index 089df92ae876..fb481f5b930a 100644 --- a/arch/riscv/mm/pmem.c +++ b/arch/riscv/mm/pmem.c @@ -7,15 +7,28 @@ #include #include +#include void arch_wb_cache_pmem(void *addr, size_t size) { +#ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS + if (unlikely(noncoherent_cache_ops.clean)) { + noncoherent_cache_ops.clean(virt_to_phys(addr), size); + return; + } +#endif ALT_CMO_OP(clean, addr, size, riscv_cbom_block_size); } EXPORT_SYMBOL_GPL(arch_wb_cache_pmem); void arch_invalidate_pmem(void *addr, size_t size) { +#ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS + if (unlikely(noncoherent_cache_ops.inval)) { + noncoherent_cache_ops.inval(virt_to_phys(addr), size); + return; + } +#endif ALT_CMO_OP(inval, addr, size, riscv_cbom_block_size); } EXPORT_SYMBOL_GPL(arch_invalidate_pmem);