From patchwork Fri Jun 30 15:48:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daire McNamara X-Patchwork-Id: 13298421 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4D67CEB64D7 for ; Fri, 30 Jun 2023 15:49:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=aweofDYkqO3EJMstw3R5vdfsoPBzlUGGiK3ItJE6Bqc=; b=39GAVlZuS5kV2r xYJK1+mVLpssHieufGbYU+ArADEt9+UtCNGUY+9kRhAmhUiKJQISD7dLf/ghPalpoL4c/PaQfH829 Be7WZoHH59DSeNhlePGWCK90dMRmH1KQdLQWvj1YDd1XtctMDiDClDRXEyayUeY3AKk9w3aUkQLGQ cZ7+LFYXdQJ7Dkwr9rkh0a5pcrH7qPzeiWXed24WTzw9YB633dK/Zr5nsN6lb5rQyKBzsJQUmGKoN iNh8FjgaZ9HamvE6FaDZ9BZc93dY7qaojvT6VXWD0i03B/Gi4/0GhR+ew6GSB5Lqr2DKm8LVo0J2b w/eVZs8N6f/IHia+TRqQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qFGNM-003ysX-2M; Fri, 30 Jun 2023 15:49:36 +0000 Received: from esa.microchip.iphmx.com ([68.232.153.233]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qFGNH-003ypE-0O for linux-riscv@lists.infradead.org; Fri, 30 Jun 2023 15:49:32 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1688140170; x=1719676170; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Z3xYhVEx72Z+f9tvRKEXppzoishp+v+MhHnaBZz+XpI=; b=pFCnYiM1paaJmNFQBD2wk+VFTx+mcSyf2avD/sTsLB7rtsPrmu2PJx6h efZB5ysxUqpi623IozreTvuBAXpB364lL+MtndJvbs83LloCk5mU0de87 4DPLgRfzjvAD24thvckKm4FpNbs7eed24a98dqGqUMaU3l/ba4Z/dY07R VMFIJxs64R0JE25hM3TqdxalI8xBsPlID5d2y/MmS5DFv65PWTgFmn9Jt V+adr3kJux8C2XfPvNvtkjFzKTdNRRkCwM6lWr/OEiS/fL0GYnIbnenh7 0zxI+mBCEMxHvxI74JGyBgN2okhw9KAel+dOE3szXaCwRXmq3vag6boja A==; X-IronPort-AV: E=Sophos;i="6.01,171,1684825200"; d="scan'208";a="233133677" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 30 Jun 2023 08:49:28 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Fri, 30 Jun 2023 08:49:21 -0700 Received: from daire-X570.amer.actel.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Fri, 30 Jun 2023 08:49:19 -0700 From: To: CC: Daire McNamara , Conor Dooley , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas , , Subject: [PATCH v2 8/8] PCI: microchip: Re-partition code between probe() and init() Date: Fri, 30 Jun 2023 16:48:59 +0100 Message-ID: <20230630154859.2049521-9-daire.mcnamara@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230630154859.2049521-1-daire.mcnamara@microchip.com> References: <20230630154859.2049521-1-daire.mcnamara@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230630_084931_176293_7E4D166E X-CRM114-Status: GOOD ( 17.21 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Daire McNamara Continuing to use pci_host_common_probe() for the PCIe Root Complex on PolarFire SoC was leading to an extremely large _init() function and some unnatural code flow. Re-partition so some tasks are done in a _probe() routine, which calls pci_host_common_probe() and then use a much smaller _init() function, mainly to enable interrupts after address translation tables are set up. Signed-off-by: Daire McNamara Reviewed-by: Conor Dooley --- drivers/pci/controller/pcie-microchip-host.c | 58 +++++++++++++------- 1 file changed, 38 insertions(+), 20 deletions(-) diff --git a/drivers/pci/controller/pcie-microchip-host.c b/drivers/pci/controller/pcie-microchip-host.c index 5bb467de9cc5..2ba96d7f9095 100644 --- a/drivers/pci/controller/pcie-microchip-host.c +++ b/drivers/pci/controller/pcie-microchip-host.c @@ -383,6 +383,8 @@ static struct { static char poss_clks[][5] = { "fic0", "fic1", "fic2", "fic3" }; +static struct mc_pcie *port; + static void mc_pcie_fixup_ecam(struct mc_pcie *port, void __iomem *ecam) { struct mc_msi *msi = &port->msi; @@ -1105,7 +1107,34 @@ static int mc_platform_init(struct pci_config_window *cfg) { struct device *dev = cfg->parent; struct platform_device *pdev = to_platform_device(dev); - struct mc_pcie *port; + void __iomem *bridge_base_addr = + port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; + int ret; + + /* Configure address translation table 0 for PCIe config space */ + mc_pcie_setup_window(bridge_base_addr, 0, cfg->res.start, + cfg->res.start, + resource_size(&cfg->res)); + + /* Need some fixups in config space */ + mc_pcie_fixup_ecam(port, cfg->win); + + /* Configure non-config space outbound ranges */ + ret = mc_pcie_setup_windows(pdev, port); + if (ret) + return ret; + + /* Address translation is up; safe to enable interrupts */ + ret = mc_init_interrupts(pdev, port); + if (ret) + return ret; + + return 0; +} + +static int mc_host_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; void __iomem *bridge_base_addr; int ret; u32 val; @@ -1113,13 +1142,8 @@ static int mc_platform_init(struct pci_config_window *cfg) port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL); if (!port) return -ENOMEM; - port->dev = dev; - ret = mc_pcie_init_clks(dev); - if (ret) { - dev_err(dev, "failed to get clock resources, error %d\n", ret); - return -ENODEV; - } + port->dev = dev; port->axi_base_addr = devm_platform_ioremap_resource(pdev, 1); if (IS_ERR(port->axi_base_addr)) @@ -1141,22 +1165,16 @@ static int mc_platform_init(struct pci_config_window *cfg) port->msi.num_vectors = 1 << val; - /* Need some fixups for MSI in config space */ - mc_pcie_fixup_ecam(port, cfg->win); - /* Pick vector address from design */ port->msi.vector_phy = readl_relaxed(bridge_base_addr + IMSI_ADDR); - /* Configure Address Translation Table 0 for PCIe config space */ - mc_pcie_setup_window(bridge_base_addr, 0, cfg->res.start & 0xffffffff, - cfg->res.start, resource_size(&cfg->res)); - - ret = mc_pcie_setup_windows(pdev, port); - if (ret) - return ret; + ret = mc_pcie_init_clks(dev); + if (ret) { + dev_err(dev, "failed to get clock resources, error %d\n", ret); + return -ENODEV; + } - /* Address translation is up; safe to enable interrupts */ - return mc_init_interrupts(pdev, port); + return pci_host_common_probe(pdev); } static const struct pci_ecam_ops mc_ecam_ops = { @@ -1179,7 +1197,7 @@ static const struct of_device_id mc_pcie_of_match[] = { MODULE_DEVICE_TABLE(of, mc_pcie_of_match); static struct platform_driver mc_pcie_driver = { - .probe = pci_host_common_probe, + .probe = mc_host_probe, .driver = { .name = "microchip-pcie", .of_match_table = mc_pcie_of_match,