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Wed, 05 Jul 2023 20:32:43 -0700 (PDT) Received: from charlie.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id fk13-20020a056a003a8d00b006589cf6d88bsm239785pfb.145.2023.07.05.20.32.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Jul 2023 20:32:43 -0700 (PDT) From: Charlie Jenkins Date: Wed, 05 Jul 2023 20:30:18 -0700 Subject: [PATCH 2/3] RISC-V: Add T-Head 0.7.1 vector extension to hwprobe MIME-Version: 1.0 Message-Id: <20230705-thead_vendor_extensions-v1-2-ad6915349c4d@rivosinc.com> References: <20230705-thead_vendor_extensions-v1-0-ad6915349c4d@rivosinc.com> In-Reply-To: <20230705-thead_vendor_extensions-v1-0-ad6915349c4d@rivosinc.com> To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Paul Walmsley , Palmer Dabbelt , Albert Ou , Jonathan Corbet , charlie@rivosinc.com, evan@rivosinc.com, heiko@sntech.de, linux-doc@vger.kernel.org X-Mailer: b4 0.12.3 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230705_203245_207022_26B65FF5 X-CRM114-Status: GOOD ( 18.87 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Using vendor extensions in hwprobe, add the ability to query if the 0.7.1 vector extension is available. It is determined to be available only if the kernel is compiled with vector support, and the user is using the c906. Signed-off-by: Charlie Jenkins --- arch/riscv/Kconfig.vendor | 11 +++++++++++ arch/riscv/include/asm/extensions.h | 16 ++++++++++++++++ arch/riscv/kernel/sys_riscv.c | 20 ++++++++++++++++++++ arch/riscv/vendor_extensions/Makefile | 2 ++ arch/riscv/vendor_extensions/thead/Makefile | 8 ++++++++ arch/riscv/vendor_extensions/thead/extensions.c | 24 ++++++++++++++++++++++++ 6 files changed, 81 insertions(+) diff --git a/arch/riscv/Kconfig.vendor b/arch/riscv/Kconfig.vendor index 213ac3e6fed5..b8b9d15153eb 100644 --- a/arch/riscv/Kconfig.vendor +++ b/arch/riscv/Kconfig.vendor @@ -1,3 +1,14 @@ menu "Vendor extensions selection" +config VENDOR_EXTENSIONS_THEAD + bool "T-HEAD vendor extensions" + depends on RISCV_ALTERNATIVE + default n + help + All T-HEAD vendor extensions Kconfig depend on this Kconfig. Disabling + this Kconfig will disable all T-HEAD vendor extensions. Please say "Y" + here if your platform uses T-HEAD vendor extensions. + + Otherwise, please say "N" here to avoid unnecessary overhead. + endmenu # "Vendor extensions selection" diff --git a/arch/riscv/include/asm/extensions.h b/arch/riscv/include/asm/extensions.h new file mode 100644 index 000000000000..27ce294a3d65 --- /dev/null +++ b/arch/riscv/include/asm/extensions.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2023 by Rivos Inc. + */ +#ifndef __ASM_EXTENSIONS_H +#define __ASM_EXTENSIONS_H + +#include +#include + +#define THEAD_ISA_EXT0 (RISCV_HWPROBE_VENDOR_EXTENSION_SPACE) +#define THEAD_ISA_EXT0_V0_7_1 (1 << 0) + +int hwprobe_thead(__u64 marchid, __u64 mimpid, struct riscv_hwprobe *pair, + const struct cpumask *cpus); +#endif diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index 2351a5f7b8b1..58b12eaeaf46 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -192,6 +193,25 @@ static int hwprobe_vendor(__u64 mvendorid, struct riscv_hwprobe *pair, const struct cpumask *cpus) { switch (mvendorid) { +#ifdef CONFIG_VENDOR_EXTENSIONS_THEAD + case THEAD_VENDOR_ID: + struct riscv_hwprobe marchid = { + .key = RISCV_HWPROBE_KEY_MARCHID, + .value = 0 + }; + struct riscv_hwprobe mimpid = { + .key = RISCV_HWPROBE_KEY_MIMPID, + .value = 0 + }; + + hwprobe_arch_id(&marchid, cpus); + hwprobe_arch_id(&mimpid, cpus); + if (marchid.value != -1ULL && mimpid.value != -1ULL) + hwprobe_thead(marchid.value, mimpid.value, pair, cpus); + else + return -1; + break; +#endif default: return -1; } diff --git a/arch/riscv/vendor_extensions/Makefile b/arch/riscv/vendor_extensions/Makefile index e815895e9372..38c3e80469fd 100644 --- a/arch/riscv/vendor_extensions/Makefile +++ b/arch/riscv/vendor_extensions/Makefile @@ -1,3 +1,5 @@ ifdef CONFIG_RELOCATABLE KBUILD_CFLAGS += -fno-pie endif + +obj-$(CONFIG_VENDOR_EXTENSIONS_THEAD) += thead/ diff --git a/arch/riscv/vendor_extensions/thead/Makefile b/arch/riscv/vendor_extensions/thead/Makefile new file mode 100644 index 000000000000..7cf43c629b66 --- /dev/null +++ b/arch/riscv/vendor_extensions/thead/Makefile @@ -0,0 +1,8 @@ +ifdef CONFIG_FTRACE +CFLAGS_REMOVE_extensions.o = $(CC_FLAGS_FTRACE) +endif +ifdef CONFIG_KASAN +KASAN_SANITIZE_extensions.o := n +endif + +obj-y += extensions.o diff --git a/arch/riscv/vendor_extensions/thead/extensions.c b/arch/riscv/vendor_extensions/thead/extensions.c new file mode 100644 index 000000000000..a177501bc99c --- /dev/null +++ b/arch/riscv/vendor_extensions/thead/extensions.c @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023 by Rivos Inc. + */ + +#include + +int hwprobe_thead(__u64 marchid, __u64 mimpid, struct riscv_hwprobe *pair, + const struct cpumask *cpus) +{ + pair->value = 0; + switch (pair->key) { + case THEAD_ISA_EXT0: +#ifdef CONFIG_RISCV_ISA_V + if (marchid == 0 && mimpid == 0) + pair->value |= THEAD_ISA_EXT0_V0_7_1; +#endif + break; + default: + return -1; + } + + return 0; +}