From patchwork Tue Jul 11 17:17:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 13309229 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 953EAEB64DD for ; Tue, 11 Jul 2023 17:18:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=sHnoBppsCRoMKF96RS8LVf3IXATYs0I7hDmNavKoPg8=; b=mifBaNB3xvyDQM 2Rm7i3cbO2QJwgpWZFGpxLxyBhqifQLXbiA8P9Q704FP56BZYoda3X11awY3khMFBUsvUlNu9qNA1 Q+jkwYpa0S51jCFW3LWFUWem4WQNKK24TJgs7TWVRf0c3q4MIM7EN+oFb+9vEGkMTr1H6vukemSLm yWbQr6Yf0lbuDv1fODaN5L84gyxNPrRESzSRd191ZXAuSg648582Xqb9KRzA8ijLrmELcMpR8pCQ/ gxq27hjX8JwAKUK8nPt8wj4gK6zcp5z3YZ3gPFg4SvX+dgwgYzJL7/IkH5Lugj51X3bdWx5bhzLEa sUyOQ5EMVpeVmrBunkTw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qJH0O-00FUnz-28; Tue, 11 Jul 2023 17:18:28 +0000 Received: from mga04.intel.com ([192.55.52.120]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qJH0J-00FUlw-2o; Tue, 11 Jul 2023 17:18:25 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1689095903; x=1720631903; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=RLWyOf9cyhaU0D1jsbC/OzTSXA7cpjUrGSZFXoDODls=; b=YdCPukQclSdZpVbFprtKi2oDSPWqCR1oVPYrKEk13RVUb4aFZ5kwTVuR T2b8Q/W8kISChE3im9XgJSZNEn1d3tUvBmcjbZa2sqoPQhueDPTqKexx5 jKBRQ4lyVAP+UQaWxnp+phRoTVvwqqnf+9IOsfxQvggaPtG3tJ6eCrsxo cl0+LemmPf8jv02VNGX/NxOyJnBQ8wSCHG80B+LsKiHeVF1/IUHyRGfmc fBN07IWzhJXXYWbfoYYtT+yXJornVAE1ku4g/IrTcgNkPS800jUIPmmRy gRLAvzUlOMLVnPTjeE5E0vjpKC+6tOJvcOHq6jpH2QxeA8ZrAxLkXWDjR g==; X-IronPort-AV: E=McAfee;i="6600,9927,10768"; a="363545679" X-IronPort-AV: E=Sophos;i="6.01,197,1684825200"; d="scan'208";a="363545679" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jul 2023 10:18:19 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10768"; a="756427035" X-IronPort-AV: E=Sophos;i="6.01,197,1684825200"; d="scan'208";a="756427035" Received: from black.fi.intel.com ([10.237.72.28]) by orsmga001.jf.intel.com with ESMTP; 11 Jul 2023 10:18:07 -0700 Received: by black.fi.intel.com (Postfix, from userid 1003) id CE41177B; Tue, 11 Jul 2023 20:17:59 +0300 (EEST) From: Andy Shevchenko To: Mark Brown , Cristian Ciocaltea , Yang Yingliang , Andy Shevchenko , Amit Kumar Mahapatra via Alsa-devel , Serge Semin , Neil Armstrong , Tharun Kumar P , Vijaya Krishna Nivarthi , =?utf-8?q?Uwe_Kleine-K?= =?utf-8?q?=C3=B6nig?= , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-riscv@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-trace-kernel@vger.kernel.org, netdev@vger.kernel.org Cc: Sanjay R Mehta , Radu Pirea , Nicolas Ferre , Alexandre Belloni , Claudiu Beznea , Tudor Ambarus , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Matthias Brugger , AngeloGioacchino Del Regno , Andy Gross , Bjorn Andersson , Konrad Dybcio , Heiko Stuebner , Palmer Dabbelt , Paul Walmsley , Orson Zhai , Baolin Wang , Chunyan Zhang , Alain Volmat , Maxime Coquelin , Alexandre Torgue , Max Filippov , Steven Rostedt , Masami Hiramatsu , Richard Cochran , Sebastian Reichel Subject: [PATCH v3 12/14] spi: Rename SPI_MASTER_GPIO_SS to SPI_CONTROLLER_GPIO_SS Date: Tue, 11 Jul 2023 20:17:54 +0300 Message-Id: <20230711171756.86736-13-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.40.0.1.gaa8946217a0b In-Reply-To: <20230711171756.86736-1-andriy.shevchenko@linux.intel.com> References: <20230711171756.86736-1-andriy.shevchenko@linux.intel.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230711_101823_921116_1B16F951 X-CRM114-Status: GOOD ( 23.86 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Rename SPI_MASTER_GPIO_SS to SPI_CONTROLLER_GPIO_SS and convert the code to using SPI_CONTROLLER_GPIO_SS to follow the new naming schema. Signed-off-by: Andy Shevchenko Reviewed-by: Serge Semin # DW APB/AHB SSI --- drivers/spi/spi-ath79.c | 2 +- drivers/spi/spi-atmel.c | 2 +- drivers/spi/spi-bitbang.c | 6 +++--- drivers/spi/spi-davinci.c | 2 +- drivers/spi/spi-dw-core.c | 2 +- drivers/spi/spi-gpio.c | 2 +- drivers/spi/spi-imx.c | 2 +- drivers/spi/spi-orion.c | 2 +- drivers/spi/spi-rockchip.c | 2 +- drivers/spi/spi-sifive.c | 2 +- drivers/spi/spi.c | 4 ++-- include/linux/spi/spi.h | 3 +-- 12 files changed, 15 insertions(+), 16 deletions(-) diff --git a/drivers/spi/spi-ath79.c b/drivers/spi/spi-ath79.c index d3dd21386f12..1b6d977d111c 100644 --- a/drivers/spi/spi-ath79.c +++ b/drivers/spi/spi-ath79.c @@ -185,7 +185,7 @@ static int ath79_spi_probe(struct platform_device *pdev) host->use_gpio_descriptors = true; host->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32); - host->flags = SPI_MASTER_GPIO_SS; + host->flags = SPI_CONTROLLER_GPIO_SS; host->num_chipselect = 3; host->mem_ops = &ath79_mem_ops; diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c index 0865993005b2..9674499ed0a6 100644 --- a/drivers/spi/spi-atmel.c +++ b/drivers/spi/spi-atmel.c @@ -1476,7 +1476,7 @@ static int atmel_spi_probe(struct platform_device *pdev) host->num_chipselect = 4; host->setup = atmel_spi_setup; host->flags = (SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX | - SPI_MASTER_GPIO_SS); + SPI_CONTROLLER_GPIO_SS); host->transfer_one = atmel_spi_one_transfer; host->set_cs = atmel_spi_set_cs; host->cleanup = atmel_spi_cleanup; diff --git a/drivers/spi/spi-bitbang.c b/drivers/spi/spi-bitbang.c index 862f209cada1..ecd44016c197 100644 --- a/drivers/spi/spi-bitbang.c +++ b/drivers/spi/spi-bitbang.c @@ -349,11 +349,11 @@ int spi_bitbang_init(struct spi_bitbang *bitbang) /* * We only need the chipselect callback if we are actually using it. * If we just use GPIO descriptors, it is surplus. If the - * SPI_MASTER_GPIO_SS flag is set, we always need to call the + * SPI_CONTROLLER_GPIO_SS flag is set, we always need to call the * driver-specific chipselect routine. */ custom_cs = (!master->use_gpio_descriptors || - (master->flags & SPI_MASTER_GPIO_SS)); + (master->flags & SPI_CONTROLLER_GPIO_SS)); if (custom_cs && !bitbang->chipselect) return -EINVAL; @@ -371,7 +371,7 @@ int spi_bitbang_init(struct spi_bitbang *bitbang) master->transfer_one = spi_bitbang_transfer_one; /* * When using GPIO descriptors, the ->set_cs() callback doesn't even - * get called unless SPI_MASTER_GPIO_SS is set. + * get called unless SPI_CONTROLLER_GPIO_SS is set. */ if (custom_cs) master->set_cs = spi_bitbang_set_cs; diff --git a/drivers/spi/spi-davinci.c b/drivers/spi/spi-davinci.c index 014392459d5e..7ea2ac053052 100644 --- a/drivers/spi/spi-davinci.c +++ b/drivers/spi/spi-davinci.c @@ -939,7 +939,7 @@ static int davinci_spi_probe(struct platform_device *pdev) master->bus_num = pdev->id; master->num_chipselect = pdata->num_chipselect; master->bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 16); - master->flags = SPI_CONTROLLER_MUST_RX | SPI_MASTER_GPIO_SS; + master->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_GPIO_SS; master->setup = davinci_spi_setup; master->cleanup = davinci_spi_cleanup; master->can_dma = davinci_spi_can_dma; diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c index a8ba41ad4541..45f5acc26b1d 100644 --- a/drivers/spi/spi-dw-core.c +++ b/drivers/spi/spi-dw-core.c @@ -932,7 +932,7 @@ int dw_spi_add_host(struct device *dev, struct dw_spi *dws) if (dws->mem_ops.exec_op) master->mem_ops = &dws->mem_ops; master->max_speed_hz = dws->max_freq; - master->flags = SPI_MASTER_GPIO_SS; + master->flags = SPI_CONTROLLER_GPIO_SS; master->auto_runtime_pm = true; /* Get default rx sample delay */ diff --git a/drivers/spi/spi-gpio.c b/drivers/spi/spi-gpio.c index 85e149ec2910..612db477ad12 100644 --- a/drivers/spi/spi-gpio.c +++ b/drivers/spi/spi-gpio.c @@ -434,7 +434,7 @@ static int spi_gpio_probe(struct platform_device *pdev) * line, that we need to do on selection. This makes the local * callback for chipselect always get called. */ - master->flags |= SPI_MASTER_GPIO_SS; + master->flags |= SPI_CONTROLLER_GPIO_SS; bb->chipselect = spi_gpio_chipselect; bb->set_line_direction = spi_gpio_set_direction; diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c index 528ae46c087f..8d97f2b32c2b 100644 --- a/drivers/spi/spi-imx.c +++ b/drivers/spi/spi-imx.c @@ -1779,7 +1779,7 @@ static int spi_imx_probe(struct platform_device *pdev) if (is_imx51_ecspi(spi_imx) || is_imx53_ecspi(spi_imx)) { controller->max_native_cs = 4; - controller->flags |= SPI_MASTER_GPIO_SS; + controller->flags |= SPI_CONTROLLER_GPIO_SS; } spi_imx->spi_drctl = spi_drctl; diff --git a/drivers/spi/spi-orion.c b/drivers/spi/spi-orion.c index ad9e83e34297..4882aafd0505 100644 --- a/drivers/spi/spi-orion.c +++ b/drivers/spi/spi-orion.c @@ -677,7 +677,7 @@ static int orion_spi_probe(struct platform_device *pdev) master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16); master->auto_runtime_pm = true; master->use_gpio_descriptors = true; - master->flags = SPI_MASTER_GPIO_SS; + master->flags = SPI_CONTROLLER_GPIO_SS; platform_set_drvdata(pdev, master); diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c index 143ede958ac1..a37943847e81 100644 --- a/drivers/spi/spi-rockchip.c +++ b/drivers/spi/spi-rockchip.c @@ -858,7 +858,7 @@ static int rockchip_spi_probe(struct platform_device *pdev) ctlr->mode_bits |= SPI_NO_CS; ctlr->slave_abort = rockchip_spi_slave_abort; } else { - ctlr->flags = SPI_MASTER_GPIO_SS; + ctlr->flags = SPI_CONTROLLER_GPIO_SS; ctlr->max_native_cs = ROCKCHIP_SPI_MAX_CS_NUM; /* * rk spi0 has two native cs, spi1..5 one cs only diff --git a/drivers/spi/spi-sifive.c b/drivers/spi/spi-sifive.c index dae9e097c333..2f77dae85386 100644 --- a/drivers/spi/spi-sifive.c +++ b/drivers/spi/spi-sifive.c @@ -379,7 +379,7 @@ static int sifive_spi_probe(struct platform_device *pdev) * we need to "left-align" the bits (unless SPI_LSB_FIRST) */ master->bits_per_word_mask = SPI_BPW_MASK(8); - master->flags = SPI_CONTROLLER_MUST_TX | SPI_MASTER_GPIO_SS; + master->flags = SPI_CONTROLLER_MUST_TX | SPI_CONTROLLER_GPIO_SS; master->prepare_message = sifive_spi_prepare_message; master->set_cs = sifive_spi_set_cs; master->transfer_one = sifive_spi_transfer_one; diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index 9b096cbc9926..0612610a091a 100644 --- a/drivers/spi/spi.c +++ b/drivers/spi/spi.c @@ -986,7 +986,7 @@ static void spi_set_cs(struct spi_device *spi, bool enable, bool force) gpiod_set_value_cansleep(spi_get_csgpiod(spi, 0), activate); } /* Some SPI masters need both GPIO CS & slave_select */ - if ((spi->controller->flags & SPI_MASTER_GPIO_SS) && + if ((spi->controller->flags & SPI_CONTROLLER_GPIO_SS) && spi->controller->set_cs) spi->controller->set_cs(spi, !enable); } else if (spi->controller->set_cs) { @@ -3035,7 +3035,7 @@ static int spi_get_gpio_descs(struct spi_controller *ctlr) ctlr->unused_native_cs = ffs(~native_cs_mask) - 1; - if ((ctlr->flags & SPI_MASTER_GPIO_SS) && num_cs_gpios && + if ((ctlr->flags & SPI_CONTROLLER_GPIO_SS) && num_cs_gpios && ctlr->max_native_cs && ctlr->unused_native_cs >= ctlr->max_native_cs) { dev_err(dev, "No unused native chip select available\n"); return -EINVAL; diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h index b90c53332909..458369939fa5 100644 --- a/include/linux/spi/spi.h +++ b/include/linux/spi/spi.h @@ -563,8 +563,7 @@ struct spi_controller { #define SPI_CONTROLLER_NO_TX BIT(2) /* Can't do buffer write */ #define SPI_CONTROLLER_MUST_RX BIT(3) /* Requires rx */ #define SPI_CONTROLLER_MUST_TX BIT(4) /* Requires tx */ - -#define SPI_MASTER_GPIO_SS BIT(5) /* GPIO CS must select slave */ +#define SPI_CONTROLLER_GPIO_SS BIT(5) /* GPIO CS must select slave */ /* Flag indicating if the allocation of this struct is devres-managed */ bool devm_allocated;