| Message ID | 20230814205719.79647-4-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive) |
|---|---|
| State | Superseded, archived |
| Headers | show |
| Series | Add non-coherent DMA support for AX45MP | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/tree_selection | fail | Failed to apply to next/pending-fixes, riscv/for-next or riscv/master |
On Mon, 14 Aug 2023 at 23:00, Prabhakar <prabhakar.csengg@gmail.com> wrote: > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Introduce support for nonstandard noncoherent systems in the RISC-V > architecture. It enables function pointer support to handle cache > management in such systems. > > This patch adds a new configuration option called > "RISCV_NONSTANDARD_CACHE_OPS." This option is a boolean flag that > depends on "RISCV_DMA_NONCOHERENT" and enables the function pointer > support for cache management in nonstandard noncoherent systems. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > Reviewed-by: Conor Dooley <conor.dooley@microchip.com> > Tested-by: Conor Dooley <conor.dooley@microchip.com> # tyre-kicking on a d1 > --- > v10 -> v11 > * Changed data type of size from unsigned long to size_t > * Reworded doc for struct riscv_cache_ops > > v9 -> v10 > * Added __ro_after_init compiler attribute for noncoherent_cache_ops > * Renamed clean -> wback > * Renamed inval -> inv > * Renamed flush -> wback_inv > > v8 -> v9 > * New patch > --- > arch/riscv/Kconfig | 7 ++++ > arch/riscv/include/asm/dma-noncoherent.h | 28 +++++++++++++++ > arch/riscv/mm/dma-noncoherent.c | 43 ++++++++++++++++++++++++ > arch/riscv/mm/pmem.c | 13 +++++++ > 4 files changed, 91 insertions(+) > create mode 100644 arch/riscv/include/asm/dma-noncoherent.h > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > index f52dd125ac5e..a629d383affb 100644 > --- a/arch/riscv/Kconfig > +++ b/arch/riscv/Kconfig > @@ -269,6 +269,13 @@ config RISCV_DMA_NONCOHERENT > select ARCH_HAS_SYNC_DMA_FOR_DEVICE > select DMA_DIRECT_REMAP > > +config RISCV_NONSTANDARD_CACHE_OPS > + bool > + depends on RISCV_DMA_NONCOHERENT > + help > + This enables function pointer support for non-standard noncoherent > + systems to handle cache management. > + > config AS_HAS_INSN > def_bool $(as-instr,.insn r 51$(comma) 0$(comma) 0$(comma) t0$(comma) t0$(comma) zero) > > diff --git a/arch/riscv/include/asm/dma-noncoherent.h b/arch/riscv/include/asm/dma-noncoherent.h > new file mode 100644 > index 000000000000..2fc43f73f766 > --- /dev/null > +++ b/arch/riscv/include/asm/dma-noncoherent.h > @@ -0,0 +1,28 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * Copyright (C) 2023 Renesas Electronics Corp. > + */ > + > +#ifndef __ASM_DMA_NONCOHERENT_H > +#define __ASM_DMA_NONCOHERENT_H > + > +#include <linux/dma-direct.h> > + > +/* > + * struct riscv_nonstd_cache_ops - Structure for non-standard CMO function pointers It seems you updated the name in this comment.. > + * > + * @wback: Function pointer for cache writeback > + * @inv: Function pointer for invalidating cache > + * @wback_inv: Function pointer for flushing the cache (writeback + invalidating) > + */ > +struct riscv_cache_ops { ..but not the actual struct. I don't have any opinion on which is the best name, but they should probably match. > + void (*wback)(phys_addr_t paddr, size_t size); > + void (*inv)(phys_addr_t paddr, size_t size); > + void (*wback_inv)(phys_addr_t paddr, size_t size); > +}; > + > +extern struct riscv_cache_ops noncoherent_cache_ops; > + > +void riscv_noncoherent_register_cache_ops(const struct riscv_cache_ops *ops); > + > +#endif /* __ASM_DMA_NONCOHERENT_H */ > diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoherent.c > index b6a1e9cc9339..853446525a19 100644 > --- a/arch/riscv/mm/dma-noncoherent.c > +++ b/arch/riscv/mm/dma-noncoherent.c > @@ -9,13 +9,26 @@ > #include <linux/dma-map-ops.h> > #include <linux/mm.h> > #include <asm/cacheflush.h> > +#include <asm/dma-noncoherent.h> > > static bool noncoherent_supported __ro_after_init; > > +struct riscv_cache_ops noncoherent_cache_ops __ro_after_init = { > + .wback = NULL, > + .inv = NULL, > + .wback_inv = NULL, > +}; > + > static inline void arch_dma_cache_wback(phys_addr_t paddr, size_t size) > { > void *vaddr = phys_to_virt(paddr); > > +#ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS > + if (unlikely(noncoherent_cache_ops.wback)) { > + noncoherent_cache_ops.wback(paddr, size); > + return; > + } > +#endif > ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size); > } > > @@ -23,6 +36,13 @@ static inline void arch_dma_cache_inv(phys_addr_t paddr, size_t size) > { > void *vaddr = phys_to_virt(paddr); > > +#ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS > + if (unlikely(noncoherent_cache_ops.inv)) { > + noncoherent_cache_ops.inv(paddr, size); > + return; > + } > +#endif > + > ALT_CMO_OP(inval, vaddr, size, riscv_cbom_block_size); > } > > @@ -30,6 +50,13 @@ static inline void arch_dma_cache_wback_inv(phys_addr_t paddr, size_t size) > { > void *vaddr = phys_to_virt(paddr); > > +#ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS > + if (unlikely(noncoherent_cache_ops.wback_inv)) { > + noncoherent_cache_ops.wback_inv(paddr, size); > + return; > + } > +#endif > + > ALT_CMO_OP(flush, vaddr, size, riscv_cbom_block_size); > } > > @@ -49,6 +76,13 @@ void arch_dma_prep_coherent(struct page *page, size_t size) > { > void *flush_addr = page_address(page); > > +#ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS > + if (unlikely(noncoherent_cache_ops.wback_inv)) { > + noncoherent_cache_ops.wback_inv(page_to_phys(page), size); > + return; > + } > +#endif > + > ALT_CMO_OP(flush, flush_addr, size, riscv_cbom_block_size); > } > > @@ -74,3 +108,12 @@ void riscv_noncoherent_supported(void) > "Non-coherent DMA support enabled without a block size\n"); > noncoherent_supported = true; > } > + > +void riscv_noncoherent_register_cache_ops(const struct riscv_cache_ops *ops) > +{ > + if (!ops) > + return; > + > + noncoherent_cache_ops = *ops; > +} > +EXPORT_SYMBOL_GPL(riscv_noncoherent_register_cache_ops); > diff --git a/arch/riscv/mm/pmem.c b/arch/riscv/mm/pmem.c > index 089df92ae876..c5fc5ec96f6d 100644 > --- a/arch/riscv/mm/pmem.c > +++ b/arch/riscv/mm/pmem.c > @@ -7,15 +7,28 @@ > #include <linux/libnvdimm.h> > > #include <asm/cacheflush.h> > +#include <asm/dma-noncoherent.h> > > void arch_wb_cache_pmem(void *addr, size_t size) > { > +#ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS > + if (unlikely(noncoherent_cache_ops.wback)) { > + noncoherent_cache_ops.wback(virt_to_phys(addr), size); > + return; > + } > +#endif > ALT_CMO_OP(clean, addr, size, riscv_cbom_block_size); > } > EXPORT_SYMBOL_GPL(arch_wb_cache_pmem); > > void arch_invalidate_pmem(void *addr, size_t size) > { > +#ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS > + if (unlikely(noncoherent_cache_ops.inv)) { > + noncoherent_cache_ops.inv(virt_to_phys(addr), size); > + return; > + } > +#endif > ALT_CMO_OP(inval, addr, size, riscv_cbom_block_size); > } > EXPORT_SYMBOL_GPL(arch_invalidate_pmem); > -- > 2.34.1 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv
Hi Emil, Thank you for the review. On Thu, Aug 17, 2023 at 11:54 AM Emil Renner Berthing <emil.renner.berthing@canonical.com> wrote: > > On Mon, 14 Aug 2023 at 23:00, Prabhakar <prabhakar.csengg@gmail.com> wrote: > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > Introduce support for nonstandard noncoherent systems in the RISC-V > > architecture. It enables function pointer support to handle cache > > management in such systems. > > > > This patch adds a new configuration option called > > "RISCV_NONSTANDARD_CACHE_OPS." This option is a boolean flag that > > depends on "RISCV_DMA_NONCOHERENT" and enables the function pointer > > support for cache management in nonstandard noncoherent systems. > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Reviewed-by: Conor Dooley <conor.dooley@microchip.com> > > Tested-by: Conor Dooley <conor.dooley@microchip.com> # tyre-kicking on a d1 > > --- > > v10 -> v11 > > * Changed data type of size from unsigned long to size_t > > * Reworded doc for struct riscv_cache_ops > > > > v9 -> v10 > > * Added __ro_after_init compiler attribute for noncoherent_cache_ops > > * Renamed clean -> wback > > * Renamed inval -> inv > > * Renamed flush -> wback_inv > > > > v8 -> v9 > > * New patch > > --- > > arch/riscv/Kconfig | 7 ++++ > > arch/riscv/include/asm/dma-noncoherent.h | 28 +++++++++++++++ > > arch/riscv/mm/dma-noncoherent.c | 43 ++++++++++++++++++++++++ > > arch/riscv/mm/pmem.c | 13 +++++++ > > 4 files changed, 91 insertions(+) > > create mode 100644 arch/riscv/include/asm/dma-noncoherent.h > > > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > > index f52dd125ac5e..a629d383affb 100644 > > --- a/arch/riscv/Kconfig > > +++ b/arch/riscv/Kconfig > > @@ -269,6 +269,13 @@ config RISCV_DMA_NONCOHERENT > > select ARCH_HAS_SYNC_DMA_FOR_DEVICE > > select DMA_DIRECT_REMAP > > > > +config RISCV_NONSTANDARD_CACHE_OPS > > + bool > > + depends on RISCV_DMA_NONCOHERENT > > + help > > + This enables function pointer support for non-standard noncoherent > > + systems to handle cache management. > > + > > config AS_HAS_INSN > > def_bool $(as-instr,.insn r 51$(comma) 0$(comma) 0$(comma) t0$(comma) t0$(comma) zero) > > > > diff --git a/arch/riscv/include/asm/dma-noncoherent.h b/arch/riscv/include/asm/dma-noncoherent.h > > new file mode 100644 > > index 000000000000..2fc43f73f766 > > --- /dev/null > > +++ b/arch/riscv/include/asm/dma-noncoherent.h > > @@ -0,0 +1,28 @@ > > +/* SPDX-License-Identifier: GPL-2.0-only */ > > +/* > > + * Copyright (C) 2023 Renesas Electronics Corp. > > + */ > > + > > +#ifndef __ASM_DMA_NONCOHERENT_H > > +#define __ASM_DMA_NONCOHERENT_H > > + > > +#include <linux/dma-direct.h> > > + > > +/* > > + * struct riscv_nonstd_cache_ops - Structure for non-standard CMO function pointers > > It seems you updated the name in this comment.. > > > + * > > + * @wback: Function pointer for cache writeback > > + * @inv: Function pointer for invalidating cache > > + * @wback_inv: Function pointer for flushing the cache (writeback + invalidating) > > + */ > > +struct riscv_cache_ops { > > ..but not the actual struct. I don't have any opinion on which is the > best name, but they should probably match. > Argh! Thanks for pointing out that I'll fix it and resend the series. Cheers, Prabhakar > > + void (*wback)(phys_addr_t paddr, size_t size); > > + void (*inv)(phys_addr_t paddr, size_t size); > > + void (*wback_inv)(phys_addr_t paddr, size_t size); > > +}; > > + > > +extern struct riscv_cache_ops noncoherent_cache_ops; > > + > > +void riscv_noncoherent_register_cache_ops(const struct riscv_cache_ops *ops); > > + > > +#endif /* __ASM_DMA_NONCOHERENT_H */ > > diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoherent.c > > index b6a1e9cc9339..853446525a19 100644 > > --- a/arch/riscv/mm/dma-noncoherent.c > > +++ b/arch/riscv/mm/dma-noncoherent.c > > @@ -9,13 +9,26 @@ > > #include <linux/dma-map-ops.h> > > #include <linux/mm.h> > > #include <asm/cacheflush.h> > > +#include <asm/dma-noncoherent.h> > > > > static bool noncoherent_supported __ro_after_init; > > > > +struct riscv_cache_ops noncoherent_cache_ops __ro_after_init = { > > + .wback = NULL, > > + .inv = NULL, > > + .wback_inv = NULL, > > +}; > > + > > static inline void arch_dma_cache_wback(phys_addr_t paddr, size_t size) > > { > > void *vaddr = phys_to_virt(paddr); > > > > +#ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS > > + if (unlikely(noncoherent_cache_ops.wback)) { > > + noncoherent_cache_ops.wback(paddr, size); > > + return; > > + } > > +#endif > > ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size); > > } > > > > @@ -23,6 +36,13 @@ static inline void arch_dma_cache_inv(phys_addr_t paddr, size_t size) > > { > > void *vaddr = phys_to_virt(paddr); > > > > +#ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS > > + if (unlikely(noncoherent_cache_ops.inv)) { > > + noncoherent_cache_ops.inv(paddr, size); > > + return; > > + } > > +#endif > > + > > ALT_CMO_OP(inval, vaddr, size, riscv_cbom_block_size); > > } > > > > @@ -30,6 +50,13 @@ static inline void arch_dma_cache_wback_inv(phys_addr_t paddr, size_t size) > > { > > void *vaddr = phys_to_virt(paddr); > > > > +#ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS > > + if (unlikely(noncoherent_cache_ops.wback_inv)) { > > + noncoherent_cache_ops.wback_inv(paddr, size); > > + return; > > + } > > +#endif > > + > > ALT_CMO_OP(flush, vaddr, size, riscv_cbom_block_size); > > } > > > > @@ -49,6 +76,13 @@ void arch_dma_prep_coherent(struct page *page, size_t size) > > { > > void *flush_addr = page_address(page); > > > > +#ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS > > + if (unlikely(noncoherent_cache_ops.wback_inv)) { > > + noncoherent_cache_ops.wback_inv(page_to_phys(page), size); > > + return; > > + } > > +#endif > > + > > ALT_CMO_OP(flush, flush_addr, size, riscv_cbom_block_size); > > } > > > > @@ -74,3 +108,12 @@ void riscv_noncoherent_supported(void) > > "Non-coherent DMA support enabled without a block size\n"); > > noncoherent_supported = true; > > } > > + > > +void riscv_noncoherent_register_cache_ops(const struct riscv_cache_ops *ops) > > +{ > > + if (!ops) > > + return; > > + > > + noncoherent_cache_ops = *ops; > > +} > > +EXPORT_SYMBOL_GPL(riscv_noncoherent_register_cache_ops); > > diff --git a/arch/riscv/mm/pmem.c b/arch/riscv/mm/pmem.c > > index 089df92ae876..c5fc5ec96f6d 100644 > > --- a/arch/riscv/mm/pmem.c > > +++ b/arch/riscv/mm/pmem.c > > @@ -7,15 +7,28 @@ > > #include <linux/libnvdimm.h> > > > > #include <asm/cacheflush.h> > > +#include <asm/dma-noncoherent.h> > > > > void arch_wb_cache_pmem(void *addr, size_t size) > > { > > +#ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS > > + if (unlikely(noncoherent_cache_ops.wback)) { > > + noncoherent_cache_ops.wback(virt_to_phys(addr), size); > > + return; > > + } > > +#endif > > ALT_CMO_OP(clean, addr, size, riscv_cbom_block_size); > > } > > EXPORT_SYMBOL_GPL(arch_wb_cache_pmem); > > > > void arch_invalidate_pmem(void *addr, size_t size) > > { > > +#ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS > > + if (unlikely(noncoherent_cache_ops.inv)) { > > + noncoherent_cache_ops.inv(virt_to_phys(addr), size); > > + return; > > + } > > +#endif > > ALT_CMO_OP(inval, addr, size, riscv_cbom_block_size); > > } > > EXPORT_SYMBOL_GPL(arch_invalidate_pmem); > > -- > > 2.34.1 > > > > > > _______________________________________________ > > linux-riscv mailing list > > linux-riscv@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-riscv
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index f52dd125ac5e..a629d383affb 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -269,6 +269,13 @@ config RISCV_DMA_NONCOHERENT select ARCH_HAS_SYNC_DMA_FOR_DEVICE select DMA_DIRECT_REMAP +config RISCV_NONSTANDARD_CACHE_OPS + bool + depends on RISCV_DMA_NONCOHERENT + help + This enables function pointer support for non-standard noncoherent + systems to handle cache management. + config AS_HAS_INSN def_bool $(as-instr,.insn r 51$(comma) 0$(comma) 0$(comma) t0$(comma) t0$(comma) zero) diff --git a/arch/riscv/include/asm/dma-noncoherent.h b/arch/riscv/include/asm/dma-noncoherent.h new file mode 100644 index 000000000000..2fc43f73f766 --- /dev/null +++ b/arch/riscv/include/asm/dma-noncoherent.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2023 Renesas Electronics Corp. + */ + +#ifndef __ASM_DMA_NONCOHERENT_H +#define __ASM_DMA_NONCOHERENT_H + +#include <linux/dma-direct.h> + +/* + * struct riscv_nonstd_cache_ops - Structure for non-standard CMO function pointers + * + * @wback: Function pointer for cache writeback + * @inv: Function pointer for invalidating cache + * @wback_inv: Function pointer for flushing the cache (writeback + invalidating) + */ +struct riscv_cache_ops { + void (*wback)(phys_addr_t paddr, size_t size); + void (*inv)(phys_addr_t paddr, size_t size); + void (*wback_inv)(phys_addr_t paddr, size_t size); +}; + +extern struct riscv_cache_ops noncoherent_cache_ops; + +void riscv_noncoherent_register_cache_ops(const struct riscv_cache_ops *ops); + +#endif /* __ASM_DMA_NONCOHERENT_H */ diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoherent.c index b6a1e9cc9339..853446525a19 100644 --- a/arch/riscv/mm/dma-noncoherent.c +++ b/arch/riscv/mm/dma-noncoherent.c @@ -9,13 +9,26 @@ #include <linux/dma-map-ops.h> #include <linux/mm.h> #include <asm/cacheflush.h> +#include <asm/dma-noncoherent.h> static bool noncoherent_supported __ro_after_init; +struct riscv_cache_ops noncoherent_cache_ops __ro_after_init = { + .wback = NULL, + .inv = NULL, + .wback_inv = NULL, +}; + static inline void arch_dma_cache_wback(phys_addr_t paddr, size_t size) { void *vaddr = phys_to_virt(paddr); +#ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS + if (unlikely(noncoherent_cache_ops.wback)) { + noncoherent_cache_ops.wback(paddr, size); + return; + } +#endif ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size); } @@ -23,6 +36,13 @@ static inline void arch_dma_cache_inv(phys_addr_t paddr, size_t size) { void *vaddr = phys_to_virt(paddr); +#ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS + if (unlikely(noncoherent_cache_ops.inv)) { + noncoherent_cache_ops.inv(paddr, size); + return; + } +#endif + ALT_CMO_OP(inval, vaddr, size, riscv_cbom_block_size); } @@ -30,6 +50,13 @@ static inline void arch_dma_cache_wback_inv(phys_addr_t paddr, size_t size) { void *vaddr = phys_to_virt(paddr); +#ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS + if (unlikely(noncoherent_cache_ops.wback_inv)) { + noncoherent_cache_ops.wback_inv(paddr, size); + return; + } +#endif + ALT_CMO_OP(flush, vaddr, size, riscv_cbom_block_size); } @@ -49,6 +76,13 @@ void arch_dma_prep_coherent(struct page *page, size_t size) { void *flush_addr = page_address(page); +#ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS + if (unlikely(noncoherent_cache_ops.wback_inv)) { + noncoherent_cache_ops.wback_inv(page_to_phys(page), size); + return; + } +#endif + ALT_CMO_OP(flush, flush_addr, size, riscv_cbom_block_size); } @@ -74,3 +108,12 @@ void riscv_noncoherent_supported(void) "Non-coherent DMA support enabled without a block size\n"); noncoherent_supported = true; } + +void riscv_noncoherent_register_cache_ops(const struct riscv_cache_ops *ops) +{ + if (!ops) + return; + + noncoherent_cache_ops = *ops; +} +EXPORT_SYMBOL_GPL(riscv_noncoherent_register_cache_ops); diff --git a/arch/riscv/mm/pmem.c b/arch/riscv/mm/pmem.c index 089df92ae876..c5fc5ec96f6d 100644 --- a/arch/riscv/mm/pmem.c +++ b/arch/riscv/mm/pmem.c @@ -7,15 +7,28 @@ #include <linux/libnvdimm.h> #include <asm/cacheflush.h> +#include <asm/dma-noncoherent.h> void arch_wb_cache_pmem(void *addr, size_t size) { +#ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS + if (unlikely(noncoherent_cache_ops.wback)) { + noncoherent_cache_ops.wback(virt_to_phys(addr), size); + return; + } +#endif ALT_CMO_OP(clean, addr, size, riscv_cbom_block_size); } EXPORT_SYMBOL_GPL(arch_wb_cache_pmem); void arch_invalidate_pmem(void *addr, size_t size) { +#ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS + if (unlikely(noncoherent_cache_ops.inv)) { + noncoherent_cache_ops.inv(virt_to_phys(addr), size); + return; + } +#endif ALT_CMO_OP(inval, addr, size, riscv_cbom_block_size); } EXPORT_SYMBOL_GPL(arch_invalidate_pmem);