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[94.181.180.60]) by smtp.gmail.com with ESMTPSA id o17-20020a2e0c51000000b002ba053e1f9bsm534568ljd.35.2023.08.24.04.41.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Aug 2023 04:41:21 -0700 (PDT) From: Aleksandr Shubin To: linux-kernel@vger.kernel.org Subject: [PATCH v6 3/3] riscv: dts: allwinner: d1: Add pwm node Date: Thu, 24 Aug 2023 14:40:27 +0300 Message-Id: <20230824114038.891493-4-privatesub2@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230824114038.891493-1-privatesub2@gmail.com> References: <20230824114038.891493-1-privatesub2@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230824_044123_503261_B5F3C4BC X-CRM114-Status: GOOD ( 11.67 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arm-kernel@lists.infradead.org, linux-pwm@vger.kernel.org, Conor Dooley , Aleksandr Shubin , Philipp Zabel , Samuel Holland , devicetree@vger.kernel.org, Greg Kroah-Hartman , Paul Walmsley , Rob Herring , Chen-Yu Tsai , Thierry Reding , Palmer Dabbelt , Jernej Skrabec , Krzysztof Kozlowski , =?utf-8?q?Uwe_Klei?= =?utf-8?q?ne-K=C3=B6nig?= , linux-riscv@lists.infradead.org, linux-sunxi@lists.linux.dev, Albert Ou Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org D1 and T113s contain a pwm controller with 8 channels. This controller is supported by the sun20i-pwm driver. Add a device tree node for it. Signed-off-by: Aleksandr Shubin --- arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi index 922e8e0e2c09..c4ce13ab9512 100644 --- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi @@ -127,6 +127,18 @@ uart3_pb_pins: uart3-pb-pins { }; }; + pwm: pwm@2000c00 { + compatible = "allwinner,sun20i-d1-pwm"; + reg = <0x02000c00 0x400>; + clocks = <&ccu CLK_BUS_PWM>, + <&dcxo>, + <&ccu CLK_APB0>; + clock-names = "bus", "hosc", "apb0"; + resets = <&ccu RST_BUS_PWM>; + status = "disabled"; + #pwm-cells = <0x3>; + }; + ccu: clock-controller@2001000 { compatible = "allwinner,sun20i-d1-ccu"; reg = <0x2001000 0x1000>;