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([2a01:e0a:999:a3a0:2b3d:6c70:9dbf:5ede]) by smtp.gmail.com with ESMTPSA id x11-20020a5d650b000000b00318147fd2d3sm14926060wru.41.2023.09.26.08.03.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Sep 2023 08:03:54 -0700 (PDT) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Atish Patra , Andrew Jones , Evan Green , =?utf-8?q?Bj=C3=B6rn_Topel?= , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Ron Minnich , Daniel Maslowski Subject: [PATCH 3/7] riscv: report perf event for misaligned fault Date: Tue, 26 Sep 2023 17:03:12 +0200 Message-Id: <20230926150316.1129648-4-cleger@rivosinc.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230926150316.1129648-1-cleger@rivosinc.com> References: <20230926150316.1129648-1-cleger@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230926_080356_494278_F4A49AA7 X-CRM114-Status: UNSURE ( 9.81 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add missing calls to account for misaligned fault event using perf_sw_event(). Signed-off-by: Clément Léger --- arch/riscv/kernel/traps_misaligned.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c index 9daed7d756ae..804f6c5e0e44 100644 --- a/arch/riscv/kernel/traps_misaligned.c +++ b/arch/riscv/kernel/traps_misaligned.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include @@ -294,6 +295,8 @@ int handle_misaligned_load(struct pt_regs *regs) unsigned long addr = regs->badaddr; int i, fp = 0, shift = 0, len = 0; + perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr); + if (get_insn(regs, epc, &insn)) return -1; @@ -382,6 +385,8 @@ int handle_misaligned_store(struct pt_regs *regs) unsigned long addr = regs->badaddr; int i, len = 0; + perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr); + if (get_insn(regs, epc, &insn)) return -1;