From patchwork Mon Oct 9 12:08:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 13413589 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DAE40E95A8E for ; Mon, 9 Oct 2023 12:12:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References:Message-Id :MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=ikaQMB+jvSdoQnCj2EURV0/rB3c/I8JUS/XETas06Jw=; b=Lwq4hyRw6c0wU+ WbhBqHptdp5xdEGiqfxZrHchQdjfcTSqmaz0m8OcUZ236n/ajaEyXagZ7I0zEit/lfIp4fFtGiWQH BBBbeI0TaVpZInNj3c0qUBkLpXgQgdwwOHojm0fAKugORC5dqTreW6doSbZ4fzoo3zkfhPAjUqmrr bKY8HOqxFv7jVYHHggyqHsvJFfTQZ/l8rEvEHwbC2vAIs4EjLk1y+8L4/fDv0W81/hPX7B8jTdHfb W7HdoaNjI+BVRNGIb/lZVB38388kN7B+VthqecJrXsvm9lZgQCV7xxdr9zGwrRXoqsrKfDRMeArmX GUnX0WPkCV7rSUQP2awg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qpp76-00Aa9f-0b; Mon, 09 Oct 2023 12:11:56 +0000 Received: from sin.source.kernel.org ([145.40.73.55]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qpp6y-00Aa09-1m; Mon, 09 Oct 2023 12:11:53 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sin.source.kernel.org (Postfix) with ESMTP id BB587CE138A; Mon, 9 Oct 2023 12:11:46 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9380BC433C8; Mon, 9 Oct 2023 12:11:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1696853505; bh=XR/JPTU4enAJ4pcvH8p8vc1g83S1au3eNbsnIb4ywnQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=rP9e/pVEU1XRIjj2Q9uCE+vVJQiSYLoJDDmvoN3Y+fxV4PDyb0Vs8fWv5dE22EdGz B0vb94hqvciW/TEsRbokha5ZqcprcqYd4Usrcmcr+y93H4dv3DKJAP5z76Exn3fa8W QPI2YjyCvmt6N7kiuo4tZXT3emLIL5NPZKALokimQSPX+EFbD6N5Q642tmTnWEAJKJ 7VgVCJPy4ZM09WcaxWoJv7Zi7JTkaps2cE7IhSdwgsbyuLYN5uaWHbaRut0htOs6RP au6TpCRBbjfRQmVcgQG5R8QCGK7+4xIbwmdWHVFFsdzFe+q++lxMpBhENWv+eDo/c+ wD58DJP+NWIbg== From: Mark Brown Date: Mon, 09 Oct 2023 13:08:44 +0100 Subject: [PATCH v6 10/38] arm64/cpufeature: Runtime detection of Guarded Control Stack (GCS) MIME-Version: 1.0 Message-Id: <20231009-arm64-gcs-v6-10-78e55deaa4dd@kernel.org> References: <20231009-arm64-gcs-v6-0-78e55deaa4dd@kernel.org> In-Reply-To: <20231009-arm64-gcs-v6-0-78e55deaa4dd@kernel.org> To: Catalin Marinas , Will Deacon , Jonathan Corbet , Andrew Morton , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Arnd Bergmann , Oleg Nesterov , Eric Biederman , Kees Cook , Shuah Khan , "Rick P. Edgecombe" , Deepak Gupta , Ard Biesheuvel , Szabolcs Nagy Cc: "H.J. Lu" , Paul Walmsley , Palmer Dabbelt , Albert Ou , Florian Weimer , Christian Brauner , linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-fsdevel@vger.kernel.org, linux-arch@vger.kernel.org, linux-mm@kvack.org, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Brown X-Mailer: b4 0.13-dev-0438c X-Developer-Signature: v=1; a=openpgp-sha256; l=2903; i=broonie@kernel.org; h=from:subject:message-id; bh=XR/JPTU4enAJ4pcvH8p8vc1g83S1au3eNbsnIb4ywnQ=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBlI+2ZAGHqvxhmUj+PJXN+2VsAYfmovxTrEoIYjBrX 2bzDiHWJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZSPtmQAKCRAk1otyXVSH0LouB/ 4jMbLZC7D6Zl9Jb2+lm+LeAvBZcAupYd70rbx+3xkuxxpcymaCTO3zxHXISjX1SuQqDXdZ2Qr7PfGU AD2rdudrC2wAVWtVlIuvD1s8iyD5b5nIqoiQrsYKu1s6UByhZnLIrwDq8BXPLFUNVBkwd0pMBv4DVJ OSnLTLI6pOfw2BRvIdml05y4Axyxu65IveS3S9NiO7r8GE9M/+Yjsv2UB9TfMCca2oJdKaITbH+0ht xPC1Vr58uRUI6DwnycYpnuE4Hl+w2AI0CrMHY3eiChkjo0rYQHBWfhw4qqpUKruKnfZ739/1FkLGqb XWMGY3i9fPM/PuQFxByz8YwPzG371T X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231009_051148_956833_C3D65B9D X-CRM114-Status: GOOD ( 13.22 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add a cpufeature for GCS, allowing other code to conditionally support it at runtime. Signed-off-by: Mark Brown --- arch/arm64/include/asm/cpufeature.h | 6 ++++++ arch/arm64/kernel/cpufeature.c | 16 ++++++++++++++++ arch/arm64/tools/cpucaps | 1 + 3 files changed, 23 insertions(+) diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h index 5bba39376055..4a5eea41f8ed 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -831,6 +831,12 @@ static inline bool system_supports_tlb_range(void) cpus_have_const_cap(ARM64_HAS_TLB_RANGE); } +static inline bool system_supports_gcs(void) +{ + return IS_ENABLED(CONFIG_ARM64_GCS) && + cpus_have_const_cap(ARM64_HAS_GCS); +} + int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt); bool try_emulate_mrs(struct pt_regs *regs, u32 isn); diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 444a73c2e638..e247dce1759c 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -255,6 +255,8 @@ static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { }; static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = { + ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_GCS), + FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_GCS_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SME_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MPAM_frac_SHIFT, 4, 0), @@ -2220,6 +2222,12 @@ static void cpu_enable_mops(const struct arm64_cpu_capabilities *__unused) sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_MSCEn); } +static void cpu_enable_gcs(const struct arm64_cpu_capabilities *__unused) +{ + /* GCS is not currently used at EL1 */ + write_sysreg_s(0, SYS_GCSCR_EL1); +} + /* Internal helper functions to match cpu capability type */ static bool cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap) @@ -2719,6 +2727,14 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .matches = has_cpuid_feature, ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, EVT, IMP) }, + { + .desc = "Guarded Control Stack (GCS)", + .capability = ARM64_HAS_GCS, + .type = ARM64_CPUCAP_SYSTEM_FEATURE, + .cpu_enable = cpu_enable_gcs, + .matches = has_cpuid_feature, + ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, GCS, IMP) + }, {}, }; diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps index c3f06fdef609..9b470b311f29 100644 --- a/arch/arm64/tools/cpucaps +++ b/arch/arm64/tools/cpucaps @@ -27,6 +27,7 @@ HAS_ECV_CNTPOFF HAS_EPAN HAS_EVT HAS_FGT +HAS_GCS HAS_GENERIC_AUTH HAS_GENERIC_AUTH_ARCH_QARMA3 HAS_GENERIC_AUTH_ARCH_QARMA5