From patchwork Mon Oct 9 09:37:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 13413251 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3C006E95A8E for ; Mon, 9 Oct 2023 09:40:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=KKMeMARWsK85mgf5l9XEjeMylRBZz520LN+qdAh7yuY=; b=FtRG4lW1qCe2Ou qq70sFB8eBMmFLf6lcShpt41S0MPTKIVW6IgZiV+SzrMh5AjiSlRDsofYuNdJ/B6igSBFGgjjwsbk MDMDqZsvbkuJ7AS+Al2uoDX/Myv1lWtjdZJwY35FMpZOabZFT4vEz9F5uM4eSPLP70ksnTYjYb+Oh 6pCX3uTt0eOIWTEUY8hAsZAzB30JTI99WY4RasEnxLvYl8DMRT3Ncwwx9QodMlGqI2UZt+GO5PIhR kJyCTNiZeaYKZC8qKHLbNnhhNnHyXkc62hd0TaQyopSIWnrD6pfMat049KsyP4yyiBQ5G1sdNVcg/ 8QFqZbhZm2qk3f/PHSmg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qpmkS-00A7CQ-1T; Mon, 09 Oct 2023 09:40:24 +0000 Received: from esa.microchip.iphmx.com ([68.232.154.123]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qpmkP-00A7Bi-03 for linux-riscv@lists.infradead.org; Mon, 09 Oct 2023 09:40:22 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1696844420; x=1728380420; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=VMvqdOH2bfvF8b1Y4FhIf8IeIgyZ5ZAtbeMPwdNyDAA=; b=OZuKNfZZo1TXdLtbMmQz0OOb0U1COmS1Zq1v6g/GkYvtRnuLFgloaf3w kaf+YVoo8bzD8Svs/dxo1OPI6ZPxLTWzODN8zC+ddlQGLasVdizb3CpUD G1YOPDF5CePlzMPFAqtpMKkykesfPruCEuZg1mnUaBqASSqPcQChfz84D fcqkk+NeInpX/zGdKqwGYhRoyaqrxX9vfS9pdp38Pf9YBx5dfnkYIOc99 l5+7OlcvG2UHvlcxvBHlp1yZzW3tUn1h1LYnH8ypTwXmO2Yh0WqeWtHy/ WDa5q5CvwvRVMEf95Ep0saddiAVc0kbuCGD05UZYA9lbjjsNn3LVZ2eiI w==; X-CSE-ConnectionGUID: hHeZTK8qRb+XNP3M4wjW+Q== X-CSE-MsgGUID: 9qRUDNU3T6WKGVKRrO2f/g== X-ThreatScanner-Verdict: Negative X-IronPort-AV: E=Sophos;i="6.03,210,1694761200"; d="scan'208";a="176379099" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 09 Oct 2023 02:40:19 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Mon, 9 Oct 2023 02:40:10 -0700 Received: from wendy.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Mon, 9 Oct 2023 02:40:06 -0700 From: Conor Dooley To: CC: , , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Paul Walmsley" , Palmer Dabbelt , Albert Ou , Chen-Yu Tsai , "Jernej Skrabec" , Samuel Holland , Daire McNamara , Geert Uytterhoeven , Magnus Damm , "Emil Renner Berthing" , Jisheng Zhang , Guo Ren , Fu Wei , Chen Wang , , , , Subject: [PATCH v3 6/6] riscv: dts: thead: convert isa detection to new properties Date: Mon, 9 Oct 2023 10:37:50 +0100 Message-ID: <20231009-observant-placate-0e2097996244@wendy> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231009-approve-verbalize-ce9324858e76@wendy> References: <20231009-approve-verbalize-ce9324858e76@wendy> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2059; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=VMvqdOH2bfvF8b1Y4FhIf8IeIgyZ5ZAtbeMPwdNyDAA=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDKnKJ19fr9UT0lzruPzEuz93I5VqVxaGfN5XFxCzJeLdi0LR PWKZHaUsDGIcDLJiiiyJt/tapNb/cdnh3PMWZg4rE8gQBi5OAZiIdRfD/8q3zYe13YNLNjzWaeSecn /f9suhq/2PLzsU/PGoc56V7zJGhs91atHX3xpMWLTQqXxOXI9sntI90R29c3p/GdwvXB2Vxw4A X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231009_024021_154927_4530F1F2 X-CRM114-Status: UNSURE ( 8.34 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Convert the th1520 devicetrees to use the new properties "riscv,isa-base" & "riscv,isa-extensions". For compatibility with other projects, "riscv,isa" remains. Reviewed-by: Jisheng Zhang Acked-by: Guo Ren Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/thead/th1520.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi index ce708183b6f6..723f65487246 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -20,6 +20,9 @@ c910_0: cpu@0 { compatible = "thead,c910", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <0>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -41,6 +44,9 @@ c910_1: cpu@1 { compatible = "thead,c910", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <1>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -62,6 +68,9 @@ c910_2: cpu@2 { compatible = "thead,c910", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <2>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -83,6 +92,9 @@ c910_3: cpu@3 { compatible = "thead,c910", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <3>; i-cache-block-size = <64>; i-cache-size = <65536>;