From patchwork Wed Oct 11 11:14:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= X-Patchwork-Id: 13417332 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E923DCD6E63 for ; Wed, 11 Oct 2023 12:30:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=PiZNzM92/tCy7ODPXIezunt5d9tvxQCG1esrY2JHYbs=; b=qZMVmmHBMFlPS8 hOIdym2BUm/lCBzOrSaxlaejxcXFlj8eTxNU71nIBjyk2jv+HZ406hL+0C5h/s1bRl+F/Kdy31yTP A8eFozXJTiLIDDRG8P9WUkvRGdB0iaTVElFiignifEV3cEFh0qIHRTPX94RhEacG81nxH/EWZ6FKa hEAvGPSVe3KZw9BJK4HC4e3OrowqgZ4d3mFvVo8VsLGuyHObroMbKnbQTLZEBhGV+RyR/NsYe2r1M +uUVVTdLkzcJ1y51DaIh5j5B3Z0O4yRtwPkdQDAAfDAYW8hWc3sRPz2+n0aCuPdC0dS13aROnzQ7F NOejcoKnATW8/8MdPtNw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qqYMG-00FqpV-0Y; Wed, 11 Oct 2023 12:30:36 +0000 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qqXFN-00FjGU-1k for linux-riscv@lists.infradead.org; Wed, 11 Oct 2023 11:19:29 +0000 Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-406aaccb41dso18558275e9.0 for ; Wed, 11 Oct 2023 04:19:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1697023160; x=1697627960; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=zBNgr4CfRjqqsWxQ2+6f8weSNRNIv9nwhwGw5L11t7E=; b=RYaZNfxdDlIySV5aiufHoAA1WuSSoLncxrK8f1vwtjHxPElqxu2ZDF50Ea9fi7NGu2 Ph0Kv8al0GcTlc4gEu6kg2PtIS66uWx7721jQ34WfsTKJbeL6/R6ZmzDc0/njOTRgJc3 KfQ5wTLHbIBSzbnpXhR9osMMlvlWsZ9zznmd5RI4cPuqi55W5E8zw18V4+U9BC61kn8e pi1TpOOpzYOy+DUOMFHtFSv1rzYQ4PwDjH/QxWdJSdh6kMy0K6YGnGute1cdsI+0yldK ZOJaB2XOA5yLvebJNwYb8HQvYJccBf8uHoArRVzYIk/BJapLWFCjyxivRz9G1EjwsDRI 87ZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697023160; x=1697627960; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zBNgr4CfRjqqsWxQ2+6f8weSNRNIv9nwhwGw5L11t7E=; b=DdqUsoHJii41u9d8KI+Hk1msfy1e38DCvxPUxIUMkI/lyZYIyWIzD98Y/Fa+F5ksT9 QLkALJQylAVZ7l5hkmjvKthUkolJtge7995uGDCgtK4xesRLNj9rb4MpYyQzS0cqBI22 Y0+Jl+UeG48bggRs/cKRv0uCuo+ByRCOv7/EOC7mgG15ysmdFGJVlnf/TlJ3urWyzowK XMgieuIjuInZ9IFN15+wWskfG9jEVxuePEfgQKMSgpK3Aea5RN4BNElbVosq0C4JvEVH KI+Ahor9/gaKPl2SAYMiz+qe4+ZoqdVL0IxBTWgkFFjnY0xT967IMv//wVo4xgT0gunF NdzA== X-Gm-Message-State: AOJu0YzwYtwN/w5w7DgcY4b7eXjlCPIwuwylp/omvX5v+q4d/uQMUcVy aDq+asW4NJ7q36dwFmctLPQHp966owTi9uBxl4fZYg== X-Google-Smtp-Source: AGHT+IGz2OBUFL5jTgh2YCxEN7qoM5h2KX6lIy42xfQJumWv/niH0yRdWTx+Aa/sRSbVnW7ryNwO9Q== X-Received: by 2002:a05:600c:214f:b0:406:513d:738f with SMTP id v15-20020a05600c214f00b00406513d738fmr18787533wml.2.1697023159566; Wed, 11 Oct 2023 04:19:19 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:9134:b302:d8b:a200]) by smtp.gmail.com with ESMTPSA id a4-20020a05600c224400b003fe2b081661sm18945715wmm.30.2023.10.11.04.19.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Oct 2023 04:19:19 -0700 (PDT) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley Subject: [PATCH v1 06/13] riscv: hwprobe: export Zfh/Zfhmin ISA extensions Date: Wed, 11 Oct 2023 13:14:31 +0200 Message-ID: <20231011111438.909552-7-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231011111438.909552-1-cleger@rivosinc.com> References: <20231011111438.909552-1-cleger@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231011_041925_598883_8F02401F X-CRM114-Status: GOOD ( 10.74 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Export Zfh/Zfhmin ISA extensions[1] through hwprobe only if FPU support is available. [1] https://drive.google.com/file/d/1z3tQQLm5ALsAD77PM0l0CHnapxWCeVzP/view Signed-off-by: Clément Léger --- Documentation/riscv/hwprobe.rst | 6 ++++++ arch/riscv/include/uapi/asm/hwprobe.h | 2 ++ arch/riscv/kernel/sys_riscv.c | 5 +++++ 3 files changed, 13 insertions(+) diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.rst index edfed33669ea..06f49a095f19 100644 --- a/Documentation/riscv/hwprobe.rst +++ b/Documentation/riscv/hwprobe.rst @@ -125,6 +125,12 @@ The following keys are defined: * :c:macro:`RISCV_HWPROBE_EXT_ZVKT`: The Zvkt extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. + * :c:macro:`RISCV_HWPROBE_EXT_ZFH`: The Zfh extension version 1.0 is supported + as defined in the RISC-V ISA manual. + + * :c:macro:`RISCV_HWPROBE_EXT_ZFHMIN`: The Zfhmin extension version 1.0 is + supported as defined in the RISC-V ISA manual. + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance information about the selected set of processors. diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h index d868eb431cd6..c9016abf099e 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -45,6 +45,8 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZVKSH (1 << 19) #define RISCV_HWPROBE_EXT_ZVKSG (1 << 20) #define RISCV_HWPROBE_EXT_ZVKT (1 << 21) +#define RISCV_HWPROBE_EXT_ZFH (1 << 22) +#define RISCV_HWPROBE_EXT_ZFHMIN (1 << 23) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index 4f5e51c192d5..da916981934b 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -175,6 +175,11 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, CHECK_ISA_EXT(ZVKSG); CHECK_ISA_EXT(ZVKT); } + + if (has_fpu()) { + CHECK_ISA_EXT(ZFH); + CHECK_ISA_EXT(ZFHMIN); + } #undef CHECK_ISA_EXT }