[v2,1/3] pinctrl: renesas: rzg2l: Include pinmap in RZG2L_GPIO_PORT_PACK() macro

Message ID	20231017104638.201260-2-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive)
State	Superseded
Headers	show Return-Path: <linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org> From: Prabhakar <prabhakar.csengg@gmail.com> To: Geert Uytterhoeven <geert+renesas@glider.be>, Magnus Damm <magnus.damm@gmail.com>, Linus Walleij <linus.walleij@linaro.org> Cc: Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Biju Das <biju.das.jz@bp.renesas.com>, Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>, Prabhakar <prabhakar.csengg@gmail.com>, Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Subject: [PATCH v2 1/3] pinctrl: renesas: rzg2l: Include pinmap in RZG2L_GPIO_PORT_PACK() macro Date: Tue, 17 Oct 2023 11:46:36 +0100 Message-Id: <20231017104638.201260-2-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: <20231017104638.201260-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20231017104638.201260-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 Precedence: list Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" <linux-riscv-bounces@lists.infradead.org> Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org
Series	Add missing port pins for RZ/Five SoC \| expand [v2,0/3] Add missing port pins for RZ/Five SoC [v2,1/3] pinctrl: renesas: rzg2l: Include pinmap in RZG2L_GPIO_PORT_PACK() macro [v2,2/3] pinctrl: renesas: pinctrl-rzg2l: Add the missing port pins P19 to P28 [v2,3/3] riscv: dts: renesas: r9a07g043f: Update gpio-ranges property

Context	Check	Description
conchuod/vmtest-fixes-PR	fail	merge-conflict

Hi Prabhakar, kernel test robot noticed the following build warnings: [auto build test WARNING on next-20231017] [cannot apply to geert-renesas-drivers/renesas-pinctrl geert-renesas-devel/next linusw-pinctrl/devel linusw-pinctrl/for-next v6.6-rc6 v6.6-rc5 v6.6-rc4 linus/master v6.6-rc6] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Prabhakar/pinctrl-renesas-rzg2l-Include-pinmap-in-RZG2L_GPIO_PORT_PACK-macro/20231017-184850 base: next-20231017 patch link: https://lore.kernel.org/r/20231017104638.201260-2-prabhakar.mahadev-lad.rj%40bp.renesas.com patch subject: [PATCH v2 1/3] pinctrl: renesas: rzg2l: Include pinmap in RZG2L_GPIO_PORT_PACK() macro config: m68k-allyesconfig (https://download.01.org/0day-ci/archive/20231017/202310172321.wccxqLkr-lkp@intel.com/config) compiler: m68k-linux-gcc (GCC) 13.2.0 reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20231017/202310172321.wccxqLkr-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp@intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202310172321.wccxqLkr-lkp@intel.com/ All warnings (new ones prefixed by >>): In file included from include/linux/bits.h:6, from include/linux/bitops.h:6, from drivers/pinctrl/renesas/pinctrl-rzg2l.c:8: drivers/pinctrl/renesas/pinctrl-rzg2l.c: In function 'rzg2l_pinctrl_set_mux': >> include/vdso/bits.h:7:40: warning: left shift count >= width of type [-Wshift-count-overflow] 7 | #define BIT(nr) (UL(1) << (nr)) | ^~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:93:41: note: in expansion of macro 'BIT' 93 | #define RZG2L_SINGLE_PIN BIT(63) | ^~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:99:58: note: in expansion of macro 'RZG2L_SINGLE_PIN' 99 | #define RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg) ((cfg) & RZG2L_SINGLE_PIN ? \ | ^~~~~~~~~~~~~~~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:292:27: note: in expansion of macro 'RZG2L_PIN_CFG_TO_PORT_OFFSET' 292 | u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c: In function 'rzg2l_validate_gpio_pin': >> include/vdso/bits.h:7:40: warning: left shift count >= width of type [-Wshift-count-overflow] 7 | #define BIT(nr) (UL(1) << (nr)) | ^~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:93:41: note: in expansion of macro 'BIT' 93 | #define RZG2L_SINGLE_PIN BIT(63) | ^~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:99:58: note: in expansion of macro 'RZG2L_SINGLE_PIN' 99 | #define RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg) ((cfg) & RZG2L_SINGLE_PIN ? \ | ^~~~~~~~~~~~~~~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:544:19: note: in expansion of macro 'RZG2L_PIN_CFG_TO_PORT_OFFSET' 544 | u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ >> include/vdso/bits.h:7:40: warning: left shift count >= width of type [-Wshift-count-overflow] 7 | #define BIT(nr) (UL(1) << (nr)) | ^~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:93:41: note: in expansion of macro 'BIT' 93 | #define RZG2L_SINGLE_PIN BIT(63) | ^~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:99:58: note: in expansion of macro 'RZG2L_SINGLE_PIN' 99 | #define RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg) ((cfg) & RZG2L_SINGLE_PIN ? \ | ^~~~~~~~~~~~~~~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:551:20: note: in expansion of macro 'RZG2L_PIN_CFG_TO_PORT_OFFSET' 551 | if (off != RZG2L_PIN_CFG_TO_PORT_OFFSET(data)) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c: In function 'rzg2l_pinctrl_pinconf_get': >> include/vdso/bits.h:7:40: warning: left shift count >= width of type [-Wshift-count-overflow] 7 | #define BIT(nr) (UL(1) << (nr)) | ^~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:93:41: note: in expansion of macro 'BIT' 93 | #define RZG2L_SINGLE_PIN BIT(63) | ^~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:99:58: note: in expansion of macro 'RZG2L_SINGLE_PIN' 99 | #define RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg) ((cfg) & RZG2L_SINGLE_PIN ? \ | ^~~~~~~~~~~~~~~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:757:15: note: in expansion of macro 'RZG2L_PIN_CFG_TO_PORT_OFFSET' 757 | off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ >> include/vdso/bits.h:7:40: warning: left shift count >= width of type [-Wshift-count-overflow] 7 | #define BIT(nr) (UL(1) << (nr)) | ^~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:93:41: note: in expansion of macro 'BIT' 93 | #define RZG2L_SINGLE_PIN BIT(63) | ^~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:759:25: note: in expansion of macro 'RZG2L_SINGLE_PIN' 759 | if (*pin_data & RZG2L_SINGLE_PIN) { | ^~~~~~~~~~~~~~~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c: In function 'rzg2l_pinctrl_pinconf_set': >> include/vdso/bits.h:7:40: warning: left shift count >= width of type [-Wshift-count-overflow] 7 | #define BIT(nr) (UL(1) << (nr)) | ^~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:93:41: note: in expansion of macro 'BIT' 93 | #define RZG2L_SINGLE_PIN BIT(63) | ^~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:99:58: note: in expansion of macro 'RZG2L_SINGLE_PIN' 99 | #define RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg) ((cfg) & RZG2L_SINGLE_PIN ? \ | ^~~~~~~~~~~~~~~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:855:15: note: in expansion of macro 'RZG2L_PIN_CFG_TO_PORT_OFFSET' 855 | off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ >> include/vdso/bits.h:7:40: warning: left shift count >= width of type [-Wshift-count-overflow] 7 | #define BIT(nr) (UL(1) << (nr)) | ^~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:93:41: note: in expansion of macro 'BIT' 93 | #define RZG2L_SINGLE_PIN BIT(63) | ^~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:857:25: note: in expansion of macro 'RZG2L_SINGLE_PIN' 857 | if (*pin_data & RZG2L_SINGLE_PIN) { | ^~~~~~~~~~~~~~~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c: In function 'rzg2l_gpio_request': >> include/vdso/bits.h:7:40: warning: left shift count >= width of type [-Wshift-count-overflow] 7 | #define BIT(nr) (UL(1) << (nr)) | ^~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:93:41: note: in expansion of macro 'BIT' 93 | #define RZG2L_SINGLE_PIN BIT(63) | ^~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:99:58: note: in expansion of macro 'RZG2L_SINGLE_PIN' 99 | #define RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg) ((cfg) & RZG2L_SINGLE_PIN ? \ | ^~~~~~~~~~~~~~~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:1050:19: note: in expansion of macro 'RZG2L_PIN_CFG_TO_PORT_OFFSET' 1050 | u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c: In function 'rzg2l_gpio_set_direction': >> include/vdso/bits.h:7:40: warning: left shift count >= width of type [-Wshift-count-overflow] 7 | #define BIT(nr) (UL(1) << (nr)) | ^~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:93:41: note: in expansion of macro 'BIT' 93 | #define RZG2L_SINGLE_PIN BIT(63) | ^~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:99:58: note: in expansion of macro 'RZG2L_SINGLE_PIN' 99 | #define RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg) ((cfg) & RZG2L_SINGLE_PIN ? \ | ^~~~~~~~~~~~~~~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:1082:19: note: in expansion of macro 'RZG2L_PIN_CFG_TO_PORT_OFFSET' 1082 | u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c: In function 'rzg2l_gpio_get_direction': >> include/vdso/bits.h:7:40: warning: left shift count >= width of type [-Wshift-count-overflow] 7 | #define BIT(nr) (UL(1) << (nr)) | ^~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:93:41: note: in expansion of macro 'BIT' 93 | #define RZG2L_SINGLE_PIN BIT(63) | ^~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:99:58: note: in expansion of macro 'RZG2L_SINGLE_PIN' 99 | #define RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg) ((cfg) & RZG2L_SINGLE_PIN ? \ | ^~~~~~~~~~~~~~~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:1103:19: note: in expansion of macro 'RZG2L_PIN_CFG_TO_PORT_OFFSET' 1103 | u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c: In function 'rzg2l_gpio_set': >> include/vdso/bits.h:7:40: warning: left shift count >= width of type [-Wshift-count-overflow] 7 | #define BIT(nr) (UL(1) << (nr)) | ^~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:93:41: note: in expansion of macro 'BIT' 93 | #define RZG2L_SINGLE_PIN BIT(63) | ^~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:99:58: note: in expansion of macro 'RZG2L_SINGLE_PIN' 99 | #define RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg) ((cfg) & RZG2L_SINGLE_PIN ? \ | ^~~~~~~~~~~~~~~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:1134:19: note: in expansion of macro 'RZG2L_PIN_CFG_TO_PORT_OFFSET' 1134 | u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c: In function 'rzg2l_gpio_get': >> include/vdso/bits.h:7:40: warning: left shift count >= width of type [-Wshift-count-overflow] 7 | #define BIT(nr) (UL(1) << (nr)) | ^~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:93:41: note: in expansion of macro 'BIT' 93 | #define RZG2L_SINGLE_PIN BIT(63) | ^~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:99:58: note: in expansion of macro 'RZG2L_SINGLE_PIN' 99 | #define RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg) ((cfg) & RZG2L_SINGLE_PIN ? \ | ^~~~~~~~~~~~~~~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:1167:19: note: in expansion of macro 'RZG2L_PIN_CFG_TO_PORT_OFFSET' 1167 | u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c: At top level: >> include/vdso/bits.h:7:40: warning: left shift count >= width of type [-Wshift-count-overflow] 7 | #define BIT(nr) (UL(1) << (nr)) | ^~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:93:41: note: in expansion of macro 'BIT' 93 | #define RZG2L_SINGLE_PIN BIT(63) | ^~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:94:42: note: in expansion of macro 'RZG2L_SINGLE_PIN' 94 | #define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \ | ^~~~~~~~~~~~~~~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:1360:26: note: in expansion of macro 'RZG2L_SINGLE_PIN_PACK' 1360 | { "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0, | ^~~~~~~~~~~~~~~~~~~~~ >> include/vdso/bits.h:7:40: warning: left shift count >= width of type [-Wshift-count-overflow] 7 | #define BIT(nr) (UL(1) << (nr)) | ^~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:93:41: note: in expansion of macro 'BIT' 93 | #define RZG2L_SINGLE_PIN BIT(63) | ^~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:94:42: note: in expansion of macro 'RZG2L_SINGLE_PIN' 94 | #define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \ | ^~~~~~~~~~~~~~~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:1362:32: note: in expansion of macro 'RZG2L_SINGLE_PIN_PACK' 1362 | { "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x2, 0, | ^~~~~~~~~~~~~~~~~~~~~ >> include/vdso/bits.h:7:40: warning: left shift count >= width of type [-Wshift-count-overflow] 7 | #define BIT(nr) (UL(1) << (nr)) | ^~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:93:41: note: in expansion of macro 'BIT' 93 | #define RZG2L_SINGLE_PIN BIT(63) | ^~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:94:42: note: in expansion of macro 'RZG2L_SINGLE_PIN' 94 | #define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \ | ^~~~~~~~~~~~~~~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:1364:26: note: in expansion of macro 'RZG2L_SINGLE_PIN_PACK' 1364 | { "TDO", RZG2L_SINGLE_PIN_PACK(0x3, 0, | ^~~~~~~~~~~~~~~~~~~~~ >> include/vdso/bits.h:7:40: warning: left shift count >= width of type [-Wshift-count-overflow] 7 | #define BIT(nr) (UL(1) << (nr)) | ^~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:93:41: note: in expansion of macro 'BIT' 93 | #define RZG2L_SINGLE_PIN BIT(63) | ^~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:94:42: note: in expansion of macro 'RZG2L_SINGLE_PIN' 94 | #define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \ | ^~~~~~~~~~~~~~~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:1366:33: note: in expansion of macro 'RZG2L_SINGLE_PIN_PACK' 1366 | { "AUDIO_CLK1", RZG2L_SINGLE_PIN_PACK(0x4, 0, PIN_CFG_IEN) }, | ^~~~~~~~~~~~~~~~~~~~~ >> include/vdso/bits.h:7:40: warning: left shift count >= width of type [-Wshift-count-overflow] 7 | #define BIT(nr) (UL(1) << (nr)) | ^~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:93:41: note: in expansion of macro 'BIT' 93 | #define RZG2L_SINGLE_PIN BIT(63) | ^~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:94:42: note: in expansion of macro 'RZG2L_SINGLE_PIN' 94 | #define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \ | ^~~~~~~~~~~~~~~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:1367:33: note: in expansion of macro 'RZG2L_SINGLE_PIN_PACK' 1367 | { "AUDIO_CLK2", RZG2L_SINGLE_PIN_PACK(0x4, 1, PIN_CFG_IEN) }, | ^~~~~~~~~~~~~~~~~~~~~ >> include/vdso/bits.h:7:40: warning: left shift count >= width of type [-Wshift-count-overflow] 7 | #define BIT(nr) (UL(1) << (nr)) | ^~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:93:41: note: in expansion of macro 'BIT' 93 | #define RZG2L_SINGLE_PIN BIT(63) | ^~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:94:42: note: in expansion of macro 'RZG2L_SINGLE_PIN' 94 | #define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \ | ^~~~~~~~~~~~~~~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:1368:30: note: in expansion of macro 'RZG2L_SINGLE_PIN_PACK' 1368 | { "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x6, 0, | ^~~~~~~~~~~~~~~~~~~~~ >> include/vdso/bits.h:7:40: warning: left shift count >= width of type [-Wshift-count-overflow] 7 | #define BIT(nr) (UL(1) << (nr)) | ^~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:93:41: note: in expansion of macro 'BIT' 93 | #define RZG2L_SINGLE_PIN BIT(63) | ^~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:94:42: note: in expansion of macro 'RZG2L_SINGLE_PIN' 94 | #define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \ | ^~~~~~~~~~~~~~~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:1370:30: note: in expansion of macro 'RZG2L_SINGLE_PIN_PACK' 1370 | { "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x6, 1, | ^~~~~~~~~~~~~~~~~~~~~ >> include/vdso/bits.h:7:40: warning: left shift count >= width of type [-Wshift-count-overflow] 7 | #define BIT(nr) (UL(1) << (nr)) | ^~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:93:41: note: in expansion of macro 'BIT' 93 | #define RZG2L_SINGLE_PIN BIT(63) | ^~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:94:42: note: in expansion of macro 'RZG2L_SINGLE_PIN' 94 | #define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \ | ^~~~~~~~~~~~~~~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:1372:31: note: in expansion of macro 'RZG2L_SINGLE_PIN_PACK' 1372 | { "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x6, 2, | ^~~~~~~~~~~~~~~~~~~~~ include/vdso/bits.h:7:40: warning: left shift count >= width of type [-Wshift-count-overflow] 7 | #define BIT(nr) (UL(1) << (nr)) | ^~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:93:41: note: in expansion of macro 'BIT' 93 | #define RZG2L_SINGLE_PIN BIT(63) | ^~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:94:42: note: in expansion of macro 'RZG2L_SINGLE_PIN' 94 | #define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \ | ^~~~~~~~~~~~~~~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:1374:32: note: in expansion of macro 'RZG2L_SINGLE_PIN_PACK' 1374 | { "SD0_DATA0", RZG2L_SINGLE_PIN_PACK(0x7, 0, | ^~~~~~~~~~~~~~~~~~~~~ include/vdso/bits.h:7:40: warning: left shift count >= width of type [-Wshift-count-overflow] 7 | #define BIT(nr) (UL(1) << (nr)) | ^~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:93:41: note: in expansion of macro 'BIT' 93 | #define RZG2L_SINGLE_PIN BIT(63) | ^~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:94:42: note: in expansion of macro 'RZG2L_SINGLE_PIN' 94 | #define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \ | ^~~~~~~~~~~~~~~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:1376:32: note: in expansion of macro 'RZG2L_SINGLE_PIN_PACK' 1376 | { "SD0_DATA1", RZG2L_SINGLE_PIN_PACK(0x7, 1, | ^~~~~~~~~~~~~~~~~~~~~ include/vdso/bits.h:7:40: warning: left shift count >= width of type [-Wshift-count-overflow] 7 | #define BIT(nr) (UL(1) << (nr)) | ^~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:93:41: note: in expansion of macro 'BIT' 93 | #define RZG2L_SINGLE_PIN BIT(63) | ^~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:94:42: note: in expansion of macro 'RZG2L_SINGLE_PIN' 94 | #define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \ | ^~~~~~~~~~~~~~~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:1378:32: note: in expansion of macro 'RZG2L_SINGLE_PIN_PACK' 1378 | { "SD0_DATA2", RZG2L_SINGLE_PIN_PACK(0x7, 2, | ^~~~~~~~~~~~~~~~~~~~~ include/vdso/bits.h:7:40: warning: left shift count >= width of type [-Wshift-count-overflow] 7 | #define BIT(nr) (UL(1) << (nr)) | ^~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:93:41: note: in expansion of macro 'BIT' 93 | #define RZG2L_SINGLE_PIN BIT(63) | ^~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:94:42: note: in expansion of macro 'RZG2L_SINGLE_PIN' 94 | #define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \ | ^~~~~~~~~~~~~~~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:1380:32: note: in expansion of macro 'RZG2L_SINGLE_PIN_PACK' 1380 | { "SD0_DATA3", RZG2L_SINGLE_PIN_PACK(0x7, 3, | ^~~~~~~~~~~~~~~~~~~~~ include/vdso/bits.h:7:40: warning: left shift count >= width of type [-Wshift-count-overflow] 7 | #define BIT(nr) (UL(1) << (nr)) | ^~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:93:41: note: in expansion of macro 'BIT' 93 | #define RZG2L_SINGLE_PIN BIT(63) | ^~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:94:42: note: in expansion of macro 'RZG2L_SINGLE_PIN' 94 | #define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \ | ^~~~~~~~~~~~~~~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:1382:32: note: in expansion of macro 'RZG2L_SINGLE_PIN_PACK' 1382 | { "SD0_DATA4", RZG2L_SINGLE_PIN_PACK(0x7, 4, | ^~~~~~~~~~~~~~~~~~~~~ include/vdso/bits.h:7:40: warning: left shift count >= width of type [-Wshift-count-overflow] 7 | #define BIT(nr) (UL(1) << (nr)) | ^~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:93:41: note: in expansion of macro 'BIT' 93 | #define RZG2L_SINGLE_PIN BIT(63) | ^~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:94:42: note: in expansion of macro 'RZG2L_SINGLE_PIN' 94 | #define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \ | ^~~~~~~~~~~~~~~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:1384:32: note: in expansion of macro 'RZG2L_SINGLE_PIN_PACK' 1384 | { "SD0_DATA5", RZG2L_SINGLE_PIN_PACK(0x7, 5, | ^~~~~~~~~~~~~~~~~~~~~ include/vdso/bits.h:7:40: warning: left shift count >= width of type [-Wshift-count-overflow] 7 | #define BIT(nr) (UL(1) << (nr)) | ^~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:93:41: note: in expansion of macro 'BIT' 93 | #define RZG2L_SINGLE_PIN BIT(63) | ^~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:94:42: note: in expansion of macro 'RZG2L_SINGLE_PIN' 94 | #define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \ | ^~~~~~~~~~~~~~~~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:1386:32: note: in expansion of macro 'RZG2L_SINGLE_PIN_PACK' 1386 | { "SD0_DATA6", RZG2L_SINGLE_PIN_PACK(0x7, 6, | ^~~~~~~~~~~~~~~~~~~~~ include/vdso/bits.h:7:40: warning: left shift count >= width of type [-Wshift-count-overflow] 7 | #define BIT(nr) (UL(1) << (nr)) | ^~ drivers/pinctrl/renesas/pinctrl-rzg2l.c:93:41: note: in expansion of macro 'BIT' 93 | #define RZG2L_SINGLE_PIN BIT(63) vim +7 include/vdso/bits.h 3945ff37d2f48d Vincenzo Frascino 2020-03-20 6 3945ff37d2f48d Vincenzo Frascino 2020-03-20 @7 #define BIT(nr) (UL(1) << (nr)) cbdb1f163af2bb Andy Shevchenko 2022-11-28 8 #define BIT_ULL(nr) (ULL(1) << (nr)) 3945ff37d2f48d Vincenzo Frascino 2020-03-20 9

diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index e6bf66fca074..b0aeeb5ef3fa 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -80,15 +80,17 @@ * n indicates number of pins in the port, a is the register index * and f is pin configuration capabilities supported. */ -#define RZG2L_GPIO_PORT_PACK(n, a, f) (((n) << 28) | ((a) << 20) | (f)) -#define RZG2L_GPIO_PORT_GET_PINCNT(x) (((x) & GENMASK(30, 28)) >> 28) +#define RZG2L_GPIO_PORT_PACK(n, a, f) (((n) > 0 ? ((u64)(GENMASK_ULL(((n) - 1 + 28), 28))) : 0) | \ + ((a) << 20) | (f)) +#define RZG2L_GPIO_PORT_GET_PINMAP(x) (((x) & GENMASK_ULL(35, 28)) >> 28) +#define RZG2L_GPIO_PORT_GET_PINCNT(x) (hweight8(RZG2L_GPIO_PORT_GET_PINMAP((x)))) /* * BIT(31) indicates dedicated pin, p is the register index while * referencing to SR/IEN/IOLH/FILxx registers, b is the register bits * (b * 8) and f is the pin configuration capabilities supported. */ -#define RZG2L_SINGLE_PIN BIT(31) +#define RZG2L_SINGLE_PIN BIT(63) #define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \ ((p) << 24) | ((b) << 20) | (f)) #define RZG2L_SINGLE_PIN_GET_BIT(x) (((x) & GENMASK(22, 20)) >> 20) @@ -180,12 +182,12 @@ struct rzg2l_hwcfg { struct rzg2l_dedicated_configs { const char *name; - u32 config; + u64 config; }; struct rzg2l_pinctrl_data { const char * const *port_pins; - const u32 *port_pin_configs; + const u64 *port_pin_configs; unsigned int n_ports; const struct rzg2l_dedicated_configs *dedicated_pins; unsigned int n_port_pins; @@ -286,7 +288,7 @@ static int rzg2l_pinctrl_set_mux(struct pinctrl_dev *pctldev, pins = group->pins; for (i = 0; i < group->num_pins; i++) { - unsigned int *pin_data = pctrl->desc.pins[pins[i]].drv_data; + u64 *pin_data = pctrl->desc.pins[pins[i]].drv_data; u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); u32 pin = RZG2L_PIN_ID_TO_PIN(pins[i]); @@ -536,13 +538,13 @@ static int rzg2l_dt_node_to_map(struct pinctrl_dev *pctldev, } static int rzg2l_validate_gpio_pin(struct rzg2l_pinctrl *pctrl, - u32 cfg, u32 port, u8 bit) + u64 cfg, u32 port, u8 bit) { - u8 pincount = RZG2L_GPIO_PORT_GET_PINCNT(cfg); + u8 pinmap = RZG2L_GPIO_PORT_GET_PINMAP(cfg); u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg); - u32 data; + u64 data; - if (bit >= pincount || port >= pctrl->data->n_port_pins) + if (!(pinmap & BIT(bit)) || port >= pctrl->data->n_port_pins) return -EINVAL; data = pctrl->data->port_pin_configs[port]; @@ -743,7 +745,7 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, enum pin_config_param param = pinconf_to_config_param(*config); const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; - unsigned int *pin_data = pin->drv_data; + u64 *pin_data = pin->drv_data; unsigned int arg = 0; u32 off, cfg; int ret; @@ -840,7 +842,7 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; struct rzg2l_pinctrl_pin_settings settings = pctrl->settings[_pin]; - unsigned int *pin_data = pin->drv_data; + u64 *pin_data = pin->drv_data; enum pin_config_param param; unsigned int i; u32 cfg, off; @@ -1044,7 +1046,7 @@ static int rzg2l_gpio_request(struct gpio_chip *chip, unsigned int offset) { struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; - u32 *pin_data = pin_desc->drv_data; + u64 *pin_data = pin_desc->drv_data; u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); u32 port = RZG2L_PIN_ID_TO_PORT(offset); u8 bit = RZG2L_PIN_ID_TO_PIN(offset); @@ -1076,7 +1078,7 @@ static void rzg2l_gpio_set_direction(struct rzg2l_pinctrl *pctrl, u32 offset, bool output) { const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; - unsigned int *pin_data = pin_desc->drv_data; + u64 *pin_data = pin_desc->drv_data; u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); u8 bit = RZG2L_PIN_ID_TO_PIN(offset); unsigned long flags; @@ -1097,7 +1099,7 @@ static int rzg2l_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) { struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; - unsigned int *pin_data = pin_desc->drv_data; + u64 *pin_data = pin_desc->drv_data; u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); u8 bit = RZG2L_PIN_ID_TO_PIN(offset); @@ -1128,7 +1130,7 @@ static void rzg2l_gpio_set(struct gpio_chip *chip, unsigned int offset, { struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; - unsigned int *pin_data = pin_desc->drv_data; + u64 *pin_data = pin_desc->drv_data; u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); u8 bit = RZG2L_PIN_ID_TO_PIN(offset); unsigned long flags; @@ -1161,7 +1163,7 @@ static int rzg2l_gpio_get(struct gpio_chip *chip, unsigned int offset) { struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; - unsigned int *pin_data = pin_desc->drv_data; + u64 *pin_data = pin_desc->drv_data; u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); u8 bit = RZG2L_PIN_ID_TO_PIN(offset); u16 reg16; @@ -1246,7 +1248,7 @@ static const char * const rzg2l_gpio_names[] = { "P48_0", "P48_1", "P48_2", "P48_3", "P48_4", "P48_5", "P48_6", "P48_7", }; -static const u32 r9a07g044_gpio_configs[] = { +static const u64 r9a07g044_gpio_configs[] = { RZG2L_GPIO_PORT_PACK(2, 0x10, RZG2L_MPXED_PIN_FUNCS), RZG2L_GPIO_PORT_PACK(2, 0x11, RZG2L_MPXED_PIN_FUNCS), RZG2L_GPIO_PORT_PACK(2, 0x12, RZG2L_MPXED_PIN_FUNCS), @@ -1298,7 +1300,7 @@ static const u32 r9a07g044_gpio_configs[] = { RZG2L_GPIO_PORT_PACK(5, 0x40, RZG2L_MPXED_PIN_FUNCS), }; -static const u32 r9a07g043_gpio_configs[] = { +static const u64 r9a07g043_gpio_configs[] = { RZG2L_GPIO_PORT_PACK(4, 0x10, RZG2L_MPXED_PIN_FUNCS), RZG2L_GPIO_PORT_PACK(5, 0x11, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), RZG2L_GPIO_PORT_PACK(4, 0x12, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), @@ -1320,7 +1322,7 @@ static const u32 r9a07g043_gpio_configs[] = { RZG2L_GPIO_PORT_PACK(6, 0x22, RZG2L_MPXED_PIN_FUNCS), }; -static const u32 r9a08g045_gpio_configs[] = { +static const u64 r9a08g045_gpio_configs[] = { RZG2L_GPIO_PORT_PACK(4, 0x20, RZG3S_MPXED_PIN_FUNCS(A)), /* P0 */ RZG2L_GPIO_PORT_PACK(5, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | PIN_CFG_IO_VMC_ETH0)), /* P1 */ @@ -1502,7 +1504,7 @@ static void rzg2l_gpio_irq_disable(struct irq_data *d) struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip); unsigned int hwirq = irqd_to_hwirq(d); const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[hwirq]; - unsigned int *pin_data = pin_desc->drv_data; + u64 *pin_data = pin_desc->drv_data; u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); u8 bit = RZG2L_PIN_ID_TO_PIN(hwirq); unsigned long flags; @@ -1529,7 +1531,7 @@ static void rzg2l_gpio_irq_enable(struct irq_data *d) struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip); unsigned int hwirq = irqd_to_hwirq(d); const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[hwirq]; - unsigned int *pin_data = pin_desc->drv_data; + u64 *pin_data = pin_desc->drv_data; u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); u8 bit = RZG2L_PIN_ID_TO_PIN(hwirq); unsigned long flags; @@ -1748,7 +1750,7 @@ static int rzg2l_pinctrl_register(struct rzg2l_pinctrl *pctrl) const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; struct pinctrl_pin_desc *pins; unsigned int i, j; - u32 *pin_data; + u64 *pin_data; int ret; pctrl->desc.name = DRV_NAME;

[v2,1/3] pinctrl: renesas: rzg2l: Include pinmap in RZG2L_GPIO_PORT_PACK() macro

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