From patchwork Tue Oct 17 13:14:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= X-Patchwork-Id: 13425145 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F28D6CDB483 for ; Tue, 17 Oct 2023 13:15:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=r+nAd5P3KkyDyOQ1/xdSZGNwqrB4rVT6xHkMRSYr8os=; b=vkxUfRml7wULJ4 WqTpU/gsJZr7zGfPi2Yl+Xin90RZoB9ycbiaE1MfoWzOc5S9S1JyL9thDz/SiksS5UIeMN+D1CHSG JO0tjrPUFqBPAyUpJMcu8zDnGDP82IVir0eqiRPTr1x7doexnW4vV6o0nAmR3jN3nBLHFOXG69Pvu WQxJBT7vtMCyVQFO8EZyNdNIRY9ZON1fHttpvvpF6rb75grlTtLlOVhkUSWqjmST/44gmg9YyOgN2 55vRVRo7Zrmym+OcpcUVQTWqOkrkqguroO5tr7dSrYLewejg70FCezOxFXwFWWiq8/BXJRgD8746F nFECL0JFE17wLIRhy0+A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qsjvG-00CNEi-0R; Tue, 17 Oct 2023 13:15:46 +0000 Received: from mail-lj1-x22f.google.com ([2a00:1450:4864:20::22f]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qsjv7-00CN3P-0Y for linux-riscv@lists.infradead.org; Tue, 17 Oct 2023 13:15:38 +0000 Received: by mail-lj1-x22f.google.com with SMTP id 38308e7fff4ca-2c51774da07so6837811fa.1 for ; Tue, 17 Oct 2023 06:15:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1697548535; x=1698153335; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3obtZPNOKP8LH+KjJEwDeimcpj3eT+9Cd34xi+FsYNw=; b=2xEuLB20wpMosdpQY8U4UJU+ZwAVdN/P3vG5h7GycRBnwYPJPlgbYLOcLFmKJpd5kU B/CFurxXxInGyvYSQmEMPJltKA+DqdV6vIztlOG5Ex75bPwMFFoDLS3D1YFI8aFL8JoW yVvr9Q4rAPbGGbDBo/h+xIScODayoerik2TzZHWhmdzttmHoiEL2j3msMqhbO4u9VmNJ HTbJ6gWCZyY+vviLO8v7zS6YEZeh0rp01dY6lnoRS72gF124A39ntEVbbkzvPEeFaG0h vkUMbUTHi9tgpdSOYog9EysvuBVDWzdi7B7l5gTmfSaCe6bwRuhTBJ6INhANaZ1p0L3h IB7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697548535; x=1698153335; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3obtZPNOKP8LH+KjJEwDeimcpj3eT+9Cd34xi+FsYNw=; b=jcSk3OBXb5W9IFIPH8r5GjMCy3khLXZnnlaAv/ysaNzH81+uwH0ysLpayDZPIoA6JG eA1cw2dDDiMasgvWDRowtoCUwFMXMRuT2w3XQ7ugHuQq7vCCrzUSIdvA40YE8Fl5mC/i 1ECWQ1Otk+LDFv6uadsAJoronj2PWbZuW7afUJ9E40KDrlfk2e3EcBEasQ9kxt8iB5jZ adDMQal/g8MUWGFAxgPF2tpgjTJ4iNQIpHA0L0guf50B5OL/t0IG1DM32hMvlQZ0Squr 08IM/s+lOsudnmvBAvLEGEYAQVz+Ek0gn89PJmpKyO9dSC9/mdx4k/Gl7QDbBM2aUuPZ cO9g== X-Gm-Message-State: AOJu0Ywm4rS7J7E4glZz/wjNPmLMZVP7wIF3r5LshP0G1tdnNM7jDkaf U0XIT75AAH1h0T8o6otTopjhtparSjkjLHRcUysFqQ== X-Google-Smtp-Source: AGHT+IF341BXCev0oxtaNbakkAnO4ZAxajhUcsSm+LPtv73PBIJRAamKmYX/PlGez1RMG9nLGmAzPA== X-Received: by 2002:a05:651c:c8c:b0:2bf:b0d3:20f9 with SMTP id bz12-20020a05651c0c8c00b002bfb0d320f9mr1924875ljb.5.1697548535010; Tue, 17 Oct 2023 06:15:35 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:96:820c:ecf7:a817]) by smtp.gmail.com with ESMTPSA id fj7-20020a05600c0c8700b0040772138bb7sm9873393wmb.2.2023.10.17.06.15.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 06:15:34 -0700 (PDT) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley , Samuel Ortiz Subject: [PATCH v2 09/19] riscv: hwprobe: export Zfh/Zfhmin ISA extensions Date: Tue, 17 Oct 2023 15:14:46 +0200 Message-ID: <20231017131456.2053396-10-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231017131456.2053396-1-cleger@rivosinc.com> References: <20231017131456.2053396-1-cleger@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231017_061537_242175_87322462 X-CRM114-Status: GOOD ( 11.61 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Export Zfh/Zfhmin ISA extensions[1] through hwprobe only if FPU support is available. Link: https://drive.google.com/file/d/1z3tQQLm5ALsAD77PM0l0CHnapxWCeVzP/view [1] Signed-off-by: Clément Léger Reviewed-by: Evan Green --- Documentation/riscv/hwprobe.rst | 6 ++++++ arch/riscv/include/uapi/asm/hwprobe.h | 2 ++ arch/riscv/kernel/sys_riscv.c | 5 +++++ 3 files changed, 13 insertions(+) diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.rst index 8681fb601500..35aedfff5049 100644 --- a/Documentation/riscv/hwprobe.rst +++ b/Documentation/riscv/hwprobe.rst @@ -137,6 +137,12 @@ The following keys are defined: * :c:macro:`RISCV_HWPROBE_EXT_ZVKT`: The Zvkt extension is supported as defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. + * :c:macro:`RISCV_HWPROBE_EXT_ZFH`: The Zfh extension version 1.0 is supported + as defined in the RISC-V ISA manual. + + * :c:macro:`RISCV_HWPROBE_EXT_ZFHMIN`: The Zfhmin extension version 1.0 is + supported as defined in the RISC-V ISA manual. + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance information about the selected set of processors. diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h index 2529cee323db..390805c49674 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -49,6 +49,8 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZVKSED (1 << 23) #define RISCV_HWPROBE_EXT_ZVKSH (1 << 24) #define RISCV_HWPROBE_EXT_ZVKT (1 << 25) +#define RISCV_HWPROBE_EXT_ZFH (1 << 26) +#define RISCV_HWPROBE_EXT_ZFHMIN (1 << 27) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index 25d35800809f..4cca8b982a7a 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -185,6 +185,11 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, CHECK_ISA_EXT(ZVKSH); CHECK_ISA_EXT(ZVKT); } + + if (has_fpu()) { + CHECK_ISA_EXT(ZFH); + CHECK_ISA_EXT(ZFHMIN); + } #undef CHECK_ISA_EXT }