diff mbox series

[v2,17/19] riscv: add ISA extension parsing for Zfa

Message ID 20231017131456.2053396-18-cleger@rivosinc.com (mailing list archive)
State Superseded
Headers show
Series riscv: report more ISA extensions through hwprobe | expand

Checks

Context Check Description
conchuod/vmtest-for-next-PR fail PR summary
conchuod/vmtest-fixes-PR fail PR summary
conchuod/patch-17-test-1 success .github/scripts/patches/build_rv32_defconfig.sh
conchuod/patch-17-test-2 success .github/scripts/patches/build_rv64_clang_allmodconfig.sh
conchuod/patch-17-test-3 success .github/scripts/patches/build_rv64_gcc_allmodconfig.sh
conchuod/patch-17-test-4 success .github/scripts/patches/build_rv64_nommu_k210_defconfig.sh
conchuod/patch-17-test-5 success .github/scripts/patches/build_rv64_nommu_virt_defconfig.sh
conchuod/patch-17-test-6 success .github/scripts/patches/checkpatch.sh
conchuod/patch-17-test-7 success .github/scripts/patches/dtb_warn_rv64.sh
conchuod/patch-17-test-8 success .github/scripts/patches/header_inline.sh
conchuod/patch-17-test-9 success .github/scripts/patches/kdoc.sh
conchuod/patch-17-test-10 success .github/scripts/patches/module_param.sh
conchuod/patch-17-test-11 success .github/scripts/patches/verify_fixes.sh
conchuod/patch-17-test-12 success .github/scripts/patches/verify_signedoff.sh

Commit Message

Clément Léger Oct. 17, 2023, 1:14 p.m. UTC
Add parsing for Zfa ISA extension [1] which were ratified in commit
056b6ff467c7 ("Zfa is ratified") of riscv-isa-manual[2].

Link: https://drive.google.com/file/d/1VT6QIggpb59-8QRV266dEE4T8FZTxGq4/view [1]
Link: https://github.com/riscv/riscv-isa-manual/commits/056b6ff467c7 [2]
Signed-off-by: Clément Léger <cleger@rivosinc.com>
---
 arch/riscv/include/asm/hwcap.h | 1 +
 arch/riscv/kernel/cpufeature.c | 1 +
 2 files changed, 2 insertions(+)

Comments

Evan Green Oct. 18, 2023, 5:28 p.m. UTC | #1
On Tue, Oct 17, 2023 at 6:15 AM Clément Léger <cleger@rivosinc.com> wrote:
>
> Add parsing for Zfa ISA extension [1] which were ratified in commit
> 056b6ff467c7 ("Zfa is ratified") of riscv-isa-manual[2].
>
> Link: https://drive.google.com/file/d/1VT6QIggpb59-8QRV266dEE4T8FZTxGq4/view [1]
> Link: https://github.com/riscv/riscv-isa-manual/commits/056b6ff467c7 [2]
> Signed-off-by: Clément Léger <cleger@rivosinc.com>

Reviewed-by: Evan Green <evan@rivosinc.com>
diff mbox series

Patch

diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index d9fb782f198d..8f324c646a73 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -84,6 +84,7 @@ 
 #define RISCV_ISA_EXT_ZIHINTNTL		66
 #define RISCV_ISA_EXT_ZVFH		67
 #define RISCV_ISA_EXT_ZVFHMIN		68
+#define RISCV_ISA_EXT_ZFA		69
 
 #define RISCV_ISA_EXT_MAX		128
 
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index c70885f5014b..296cc0025734 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -245,6 +245,7 @@  const struct riscv_isa_ext_data riscv_isa_ext[] = {
 	__RISCV_ISA_EXT_DATA(zihintntl, RISCV_ISA_EXT_ZIHINTNTL),
 	__RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),
 	__RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM),
+	__RISCV_ISA_EXT_DATA(zfa, RISCV_ISA_EXT_ZFA),
 	__RISCV_ISA_EXT_DATA(zfh, RISCV_ISA_EXT_ZFH),
 	__RISCV_ISA_EXT_DATA(zfhmin, RISCV_ISA_EXT_ZFHMIN),
 	__RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA),