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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id l12-20020a170902f68c00b001cc0f6028b8sm2969008plg.106.2023.11.02.05.02.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Nov 2023 05:02:06 -0700 (PDT) From: Yong-Xuan Wang To: linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org Cc: greentime.hu@sifive.com, vincent.chen@sifive.com, tjytimi@163.com, alex@ghiti.fr, conor.dooley@microchip.com, ajones@ventanamicro.com, Yong-Xuan Wang , Paolo Bonzini , Shuah Khan , Paul Walmsley , Palmer Dabbelt , Albert Ou , Anup Patel , Atish Patra , Haibo Xu , kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 4/4] KVM: riscv: selftests: Add Svadu Extension to get-reg-list testt Date: Thu, 2 Nov 2023 12:01:25 +0000 Message-Id: <20231102120129.11261-5-yongxuan.wang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231102120129.11261-1-yongxuan.wang@sifive.com> References: <20231102120129.11261-1-yongxuan.wang@sifive.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231102_050210_324964_0CA0F33C X-CRM114-Status: GOOD ( 12.18 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Update the get-reg-list test to test the Svadu Extension is available for guest OS. Signed-off-by: Yong-Xuan Wang --- .../testing/selftests/kvm/riscv/get-reg-list.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c index 9f99ea42f45f..972538d76f48 100644 --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c @@ -49,6 +49,7 @@ bool filter_reg(__u64 reg) case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICSR: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIFENCEI: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIHPM: + case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SVADU: return true; /* AIA registers are always available when Ssaia can't be disabled */ case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(siselect): @@ -340,6 +341,7 @@ static const char *isa_ext_id_to_str(__u64 id) "KVM_RISCV_ISA_EXT_ZICSR", "KVM_RISCV_ISA_EXT_ZIFENCEI", "KVM_RISCV_ISA_EXT_ZIHPM", + "KVM_RISCV_ISA_EXT_SVADU", }; if (reg_off >= ARRAY_SIZE(kvm_isa_ext_reg_name)) { @@ -700,6 +702,10 @@ static __u64 fp_d_regs[] = { KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_D, }; +static __u64 svadu_regs[] = { + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SVADU, +}; + #define BASE_SUBLIST \ {"base", .regs = base_regs, .regs_n = ARRAY_SIZE(base_regs), \ .skips_set = base_skips_set, .skips_set_n = ARRAY_SIZE(base_skips_set),} @@ -739,6 +745,9 @@ static __u64 fp_d_regs[] = { #define FP_D_REGS_SUBLIST \ {"fp_d", .feature = KVM_RISCV_ISA_EXT_D, .regs = fp_d_regs, \ .regs_n = ARRAY_SIZE(fp_d_regs),} +#define SVADU_REGS_SUBLIST \ + {"svadu", .feature = KVM_RISCV_ISA_EXT_SVADU, .regs = svadu_regs, \ + .regs_n = ARRAY_SIZE(svadu_regs),} static struct vcpu_reg_list h_config = { .sublists = { @@ -876,6 +885,14 @@ static struct vcpu_reg_list fp_d_config = { }, }; +static struct vcpu_reg_list svadu_config = { + .sublists = { + BASE_SUBLIST, + SVADU_REGS_SUBLIST, + {0}, + }, +}; + struct vcpu_reg_list *vcpu_configs[] = { &h_config, &zicbom_config, @@ -894,5 +911,6 @@ struct vcpu_reg_list *vcpu_configs[] = { &aia_config, &fp_f_config, &fp_d_config, + &svadu_config, }; int vcpu_configs_n = ARRAY_SIZE(vcpu_configs);