| Message ID | 20231103090223.702340-1-cleger@rivosinc.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 22e0eb04837a63af111fae35a92f7577676b9bc8 |
| Headers | show |
| Series | riscv: fix misaligned access handling of C.SWSP and C.SDSP | expand |
Hello: This patch was applied to riscv/linux.git (fixes) by Palmer Dabbelt <palmer@rivosinc.com>: On Fri, 3 Nov 2023 10:02:23 +0100 you wrote: > This is a backport of a fix that was done in OpenSBI: ec0559eb315b > ("lib: sbi_misaligned_ldst: Fix handling of C.SWSP and C.SDSP"). > > Unlike C.LWSP/C.LDSP, these encodings can be used with the zero > register, so checking that the rs2 field is non-zero is unnecessary. > > Additionally, the previous check was incorrect since it was checking > the immediate field of the instruction instead of the rs2 field. > > [...] Here is the summary with links: - riscv: fix misaligned access handling of C.SWSP and C.SDSP https://git.kernel.org/riscv/c/22e0eb04837a You are awesome, thank you!
diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c index 378f5b151443..5348d842c745 100644 --- a/arch/riscv/kernel/traps_misaligned.c +++ b/arch/riscv/kernel/traps_misaligned.c @@ -342,16 +342,14 @@ int handle_misaligned_store(struct pt_regs *regs) } else if ((insn & INSN_MASK_C_SD) == INSN_MATCH_C_SD) { len = 8; val.data_ulong = GET_RS2S(insn, regs); - } else if ((insn & INSN_MASK_C_SDSP) == INSN_MATCH_C_SDSP && - ((insn >> SH_RD) & 0x1f)) { + } else if ((insn & INSN_MASK_C_SDSP) == INSN_MATCH_C_SDSP) { len = 8; val.data_ulong = GET_RS2C(insn, regs); #endif } else if ((insn & INSN_MASK_C_SW) == INSN_MATCH_C_SW) { len = 4; val.data_ulong = GET_RS2S(insn, regs); - } else if ((insn & INSN_MASK_C_SWSP) == INSN_MATCH_C_SWSP && - ((insn >> SH_RD) & 0x1f)) { + } else if ((insn & INSN_MASK_C_SWSP) == INSN_MATCH_C_SWSP) { len = 4; val.data_ulong = GET_RS2C(insn, regs); } else {
This is a backport of a fix that was done in OpenSBI: ec0559eb315b ("lib: sbi_misaligned_ldst: Fix handling of C.SWSP and C.SDSP"). Unlike C.LWSP/C.LDSP, these encodings can be used with the zero register, so checking that the rs2 field is non-zero is unnecessary. Additionally, the previous check was incorrect since it was checking the immediate field of the instruction instead of the rs2 field. Fixes: 956d705dd279 ("riscv: Unaligned load/store handling for M_MODE") Signed-off-by: Clément Léger <cleger@rivosinc.com> --- arch/riscv/kernel/traps_misaligned.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-)