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Wed, 22 Nov 2023 15:32:16 -0800 (PST) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id e22-20020aa78c56000000b006c875abecbcsm22603pfd.121.2023.11.22.15.32.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Nov 2023 15:32:16 -0800 (PST) From: Charlie Jenkins Date: Wed, 22 Nov 2023 15:31:42 -0800 Subject: [PATCH v3 2/2] riscv: Correct type casting in module loading MIME-Version: 1.0 Message-Id: <20231122-module_linking_freeing-v3-2-8e9e412a3305@rivosinc.com> References: <20231122-module_linking_freeing-v3-0-8e9e412a3305@rivosinc.com> In-Reply-To: <20231122-module_linking_freeing-v3-0-8e9e412a3305@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Ron Economos , Samuel Holland Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Charlie Jenkins X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1700695933; l=1122; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; bh=JEDtvtgEBmFqCKNc+NtpG6SnBh4nM+PNkCAzWthvfGI=; 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X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Use __le16 with le16_to_cpu. Fixes: 8fd6c5142395 ("riscv: Add remaining module relocations") Signed-off-by: Charlie Jenkins Reviewed-by: Samuel Holland Tested-by: Samuel Holland --- arch/riscv/kernel/module.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/riscv/kernel/module.c b/arch/riscv/kernel/module.c index fd9a5533518c..b570988e7d43 100644 --- a/arch/riscv/kernel/module.c +++ b/arch/riscv/kernel/module.c @@ -66,7 +66,7 @@ static bool riscv_insn_valid_32bit_offset(ptrdiff_t val) static int riscv_insn_rmw(void *location, u32 keep, u32 set) { - u16 *parcel = location; + __le16 *parcel = location; u32 insn = (u32)le16_to_cpu(parcel[0]) | (u32)le16_to_cpu(parcel[1]) << 16; insn &= keep; @@ -79,7 +79,7 @@ static int riscv_insn_rmw(void *location, u32 keep, u32 set) static int riscv_insn_rvc_rmw(void *location, u16 keep, u16 set) { - u16 *parcel = location; + __le16 *parcel = location; u16 insn = le16_to_cpu(*parcel); insn &= keep;