From patchwork Wed Nov 22 12:12:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yu-Chien Peter Lin X-Patchwork-Id: 13464697 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1FCD0C61D9B for ; Wed, 22 Nov 2023 12:18:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Cc:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=TcInqqO+vgddQkGMzzuw8Ju4CDx2hEIXAeEnYsYNDFU=; b=e+BrUZnFS8POGN f5EXkiLKy19zn27WbuzkPAosD9CohmvjcproeXX/NNeqc1k06x9+RzFY+TnmfPLDDkygvhTXYKeyR PwnhQMyLYMkKchRVTpXythze5ViTuWZnq/C0PWVvBGFjx9CniO1A2Xr65KkfiXw9SzwJPxhprnsIO /r12bDTGVOAFLeGdnSpPvq/y2Y1Rt7QDuANtvhK+x6f2TUgDvWmVTqPzxrQmEf+oLqPt12OL8jOnV 2gMclr02ZVTbBDd0PPdgT0en3OOmXHu2G9zv9mM20Qe/aBw1MFM5MSLVR/qaIo2Wsy2iTUUsOEMeE 0OxU371fvUJJq8DRTmOg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1r5mBB-001l0Z-0V; Wed, 22 Nov 2023 12:18:05 +0000 Received: from 60-248-80-70.hinet-ip.hinet.net ([60.248.80.70] helo=Atcsqr.andestech.com) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1r5mB1-001kr5-0I; Wed, 22 Nov 2023 12:17:56 +0000 Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 3AMCGwQb025259; Wed, 22 Nov 2023 20:16:58 +0800 (+08) (envelope-from peterlin@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Wed, 22 Nov 2023 20:16:54 +0800 From: Yu Chien Peter Lin To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v4 11/13] riscv: dts: allwinner: Add T-Head PMU extension Date: Wed, 22 Nov 2023 20:12:33 +0800 Message-ID: <20231122121235.827122-12-peterlin@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231122121235.827122-1-peterlin@andestech.com> References: <20231122121235.827122-1-peterlin@andestech.com> MIME-Version: 1.0 X-Originating-IP: [10.0.15.183] X-DNSRBL: X-MAIL: Atcsqr.andestech.com 3AMCGwQb025259 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231122_041755_582052_2BF25316 X-CRM114-Status: UNSURE ( 8.43 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org xtheadpmu stands for T-Head Performance Monitor Unit extension. Based on the added T-Head PMU ISA string, the SBI PMU driver will make use of the non-standard irq source. Signed-off-by: Yu Chien Peter Lin Reviewed-by: Guo Ren --- Changes v2 -> v3: - New patch Changes v3 -> v4: - No change --- arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi index 64c3c2e6cbe0..7dcba86cfdd0 100644 --- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi @@ -27,7 +27,7 @@ cpu0: cpu@0 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + "zifencei", "zihpm", "xtheadpmu"; #cooling-cells = <2>; cpu0_intc: interrupt-controller {