| Message ID | 20231122121235.827122-6-peterlin@andestech.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Support Andes PMU extension | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/vmtest-fixes-PR | fail | merge-conflict |
On Wed, Nov 22, 2023 at 1:16 PM Yu Chien Peter Lin <peterlin@andestech.com> wrote: > The Andes hart-level interrupt controller (Andes INTC) allows AX45MP > cores to handle custom local interrupts, such as the performance > counter overflow interrupt. > > Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert
On Wed, Nov 22, 2023 at 12:18 PM Yu Chien Peter Lin <peterlin@andestech.com> wrote: > > The Andes hart-level interrupt controller (Andes INTC) allows AX45MP > cores to handle custom local interrupts, such as the performance > counter overflow interrupt. > > Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> > --- > Changes v1 -> v2: > - New patch > Changes v2 -> v3: > - Fixed possible compatibles for Andes INTC > Changes v3 -> v4: > - No change > --- > arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Cheers, Prabhakar > diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi > index eb301d8eb2b0..78072e80793d 100644 > --- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi > +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi > @@ -38,7 +38,7 @@ cpu0: cpu@0 { > > cpu0_intc: interrupt-controller { > #interrupt-cells = <1>; > - compatible = "riscv,cpu-intc"; > + compatible = "andestech,cpu-intc", "riscv,cpu-intc"; > interrupt-controller; > }; > }; > -- > 2.34.1 > >
diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi index eb301d8eb2b0..78072e80793d 100644 --- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi @@ -38,7 +38,7 @@ cpu0: cpu@0 { cpu0_intc: interrupt-controller { #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; + compatible = "andestech,cpu-intc", "riscv,cpu-intc"; interrupt-controller; }; };
The Andes hart-level interrupt controller (Andes INTC) allows AX45MP cores to handle custom local interrupts, such as the performance counter overflow interrupt. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> --- Changes v1 -> v2: - New patch Changes v2 -> v3: - Fixed possible compatibles for Andes INTC Changes v3 -> v4: - No change --- arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)