Message ID | 20231220155723.684081-4-cleger@rivosinc.com (mailing list archive) |
---|---|
State | Accepted |
Commit | cd7be4d02f418d5d62bcaf26e5c44ceb4ce00029 |
Headers | show |
Series | riscv: hwprobe: add Zicond, Zacas and Ztso support | expand |
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index 3574a0b70be4..27beedb98198 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -171,6 +171,12 @@ properties: memory types as ratified in the 20191213 version of the privileged ISA specification. + - const: zacas + description: | + The Zacas extension for Atomic Compare-and-Swap (CAS) instructions + is supported as ratified at commit 5059e0ca641c ("update to + ratified") of the riscv-zacas. + - const: zba description: | The standard Zba bit-manipulation extension for address generation