From patchwork Tue Jan 2 06:47:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eric Biggers X-Patchwork-Id: 13508857 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DC8BCC47073 for ; Tue, 2 Jan 2024 06:50:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=iHXtvzAe7BgaUJHf40ndIZTAM9hlx7CdSkXIkee1klk=; b=q1/OQo7odXPvX1 g9TN5Dhr0s2HE/S+1IsjMimNVX8fjr1kXL6ZhTOO+1FE1giQ+5/TxzVFvhTHOlZzaQEdk2jzyEsAr UOuD8yEsuhxWmsdHA6Q33lUqWFml8Ir1/ZhahcG/vNhH0Z3Ek9m78Ihmhz7MeOA4W5O6HSOoVyw0a MtCsYxGUT3N+snHbWy6A490xLTyIgcs+pE1d1AFrwVggfmioFTC5skN83BN/VyyHH6DB8b7V5PHGn l1Kv40FKL5N7OqhbDGTdGJPiKi8T5Pqa75lL73tKg0Id1688X8NaHkLqmRJfh7UtOdvZ4zrtJ0IZJ vN4pDsZsgfCVZMrR2PSA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1rKYbY-007CGb-1f; Tue, 02 Jan 2024 06:50:24 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1rKYbV-007CFO-1t for linux-riscv@lists.infradead.org; Tue, 02 Jan 2024 06:50:22 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id D70B060FBA; Tue, 2 Jan 2024 06:50:20 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id DD24AC433C9; Tue, 2 Jan 2024 06:50:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1704178220; bh=nsJfxzeMQv5O8Qx1VjRmXPmszEADwolhj0yHfx5D/74=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=anPdWyAQc4OldYWoDG3/Qx2GKPTJX8ENGqrwU5HD3FYzCzs5gi7nGGCJhKdadGucD 6UYhGgSBEjqq/ybXUmaiGJIR5D2V7/B8r2tKyFqm6EpD/BmihHEe6HhDt4oHKpF/IE P1oOj2MN+Z/n9mzwuViN3bII9vKjRUpX47zdFe9XUI+yE/A71RQSsIXbU9OhTMZhOq gobyOSH5yprvo0759gUY71T0U6NxkOnOrsBq3+f54VmEmcSWz5ATStJ6DQ8iAi2gdJ KajkksRDzd5WVxoGP9WO1qqWMIVhUckvXhzSA4WHBISvzKaZed7GtS/9kslZHeMoSe F+gfVVZ7uBKPA== From: Eric Biggers To: linux-crypto@vger.kernel.org, linux-riscv@lists.infradead.org, Jerry Shih Cc: linux-kernel@vger.kernel.org, Ard Biesheuvel , Heiko Stuebner , Phoebe Chen , hongrong.hsu@sifive.com, Paul Walmsley , Palmer Dabbelt , Albert Ou , Andy Chiu , Heiko Stuebner Subject: [RFC PATCH 03/13] RISC-V: add helper function to read the vector VLEN Date: Tue, 2 Jan 2024 00:47:29 -0600 Message-ID: <20240102064743.220490-4-ebiggers@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240102064743.220490-1-ebiggers@kernel.org> References: <20240102064743.220490-1-ebiggers@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240101_225021_665492_BCF23C36 X-CRM114-Status: GOOD ( 11.78 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Heiko Stuebner VLEN describes the length of each vector register and some instructions need specific minimal VLENs to work correctly. The vector code already includes a variable riscv_v_vsize that contains the value of "32 vector registers with vlenb length" that gets filled during boot. vlenb is the value contained in the CSR_VLENB register and the value represents "VLEN / 8". So add riscv_vector_vlen() to return the actual VLEN value for in-kernel users when they need to check the available VLEN. Signed-off-by: Heiko Stuebner Reviewed-by: Eric Biggers Signed-off-by: Jerry Shih Signed-off-by: Eric Biggers --- arch/riscv/include/asm/vector.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h index 71af3404fda14..ae724e016fe24 100644 --- a/arch/riscv/include/asm/vector.h +++ b/arch/riscv/include/asm/vector.h @@ -218,11 +218,22 @@ static inline bool riscv_v_vstate_ctrl_user_allowed(void) { return false; } #define riscv_v_vsize (0) #define riscv_v_vstate_discard(regs) do {} while (0) #define riscv_v_vstate_save(task, regs) do {} while (0) #define riscv_v_vstate_restore(task, regs) do {} while (0) #define __switch_to_vector(__prev, __next) do {} while (0) #define riscv_v_vstate_off(regs) do {} while (0) #define riscv_v_vstate_on(regs) do {} while (0) #endif /* CONFIG_RISCV_ISA_V */ +/* + * Return the implementation's vlen value. + * + * riscv_v_vsize contains the value of "32 vector registers with vlenb length" + * so rebuild the vlen value in bits from it. + */ +static inline int riscv_vector_vlen(void) +{ + return riscv_v_vsize / 32 * 8; +} + #endif /* ! __ASM_RISCV_VECTOR_H */