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Wed, 03 Jan 2024 08:00:56 -0800 (PST) X-Google-Smtp-Source: AGHT+IH1Qw9aIClua9ds5Nw8/POsd9KwpDhXoK1ctp78/8BijwUvH1rwsQL+Vt2C/sTQWWAMNvcTuQ== X-Received: by 2002:a17:90a:c245:b0:28c:eeef:aaca with SMTP id d5-20020a17090ac24500b0028ceeefaacamr705420pjx.4.1704297655711; Wed, 03 Jan 2024 08:00:55 -0800 (PST) Received: from localhost.localdomain ([2804:431:c7ec:911:6911:ca60:846:eb46]) by smtp.gmail.com with ESMTPSA id qc8-20020a17090b288800b0028b1fce7c01sm1922253pjb.37.2024.01.03.08.00.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 08:00:55 -0800 (PST) From: Leonardo Bras To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Eric Biederman , Kees Cook , Oleg Nesterov , Leonardo Bras , Guo Ren , Andy Chiu , Conor Dooley , Xiao Wang , Vincent Chen , Charlie Jenkins , Greg Ungerer , Andrew Morton , Kemeng Shi , Alexandre Ghiti , David Hildenbrand , "Matthew Wilcox (Oracle)" , Qinglin Pan , Greentime Hu , Baoquan He , =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org Subject: [PATCH v1 1/5] riscv: Improve arch_get_mmap_end() macro Date: Wed, 3 Jan 2024 13:00:19 -0300 Message-ID: <20240103160024.70305-3-leobras@redhat.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240103160024.70305-2-leobras@redhat.com> References: <20240103160024.70305-2-leobras@redhat.com> MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240103_080105_322969_B511A162 X-CRM114-Status: GOOD ( 13.37 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org This macro caused me some confusion, which took some reviewer's time to make it clear, so I propose adding a short comment in code to avoid confusion in the future. Also, added some improvements to the macro, such as removing the assumption of VA_USER_SV57 being the largest address space. Signed-off-by: Leonardo Bras Reviewed-by: Guo Ren --- arch/riscv/include/asm/processor.h | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h index f19f861cda549..2278e2a8362af 100644 --- a/arch/riscv/include/asm/processor.h +++ b/arch/riscv/include/asm/processor.h @@ -18,15 +18,21 @@ #define DEFAULT_MAP_WINDOW (UL(1) << (MMAP_VA_BITS - 1)) #define STACK_TOP_MAX TASK_SIZE_64 +/* + * addr is a hint to the maximum userspace address that mmap should provide, so + * this macro needs to return the largest address space available so that + * mmap_end < addr, being mmap_end the top of that address space. + * See Documentation/arch/riscv/vm-layout.rst for more details. + */ #define arch_get_mmap_end(addr, len, flags) \ ({ \ unsigned long mmap_end; \ typeof(addr) _addr = (addr); \ if ((_addr) == 0 || (IS_ENABLED(CONFIG_COMPAT) && is_compat_task())) \ mmap_end = STACK_TOP_MAX; \ - else if ((_addr) >= VA_USER_SV57) \ - mmap_end = STACK_TOP_MAX; \ - else if ((((_addr) >= VA_USER_SV48)) && (VA_BITS >= VA_BITS_SV48)) \ + else if (((_addr) >= VA_USER_SV57) && (VA_BITS >= VA_BITS_SV57)) \ + mmap_end = VA_USER_SV57; \ + else if (((_addr) >= VA_USER_SV48) && (VA_BITS >= VA_BITS_SV48)) \ mmap_end = VA_USER_SV48; \ else \ mmap_end = VA_USER_SV39; \