From patchwork Mon Jan 29 09:25:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yu Chien Peter Lin X-Patchwork-Id: 13535283 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1A099C47DA9 for ; Mon, 29 Jan 2024 09:27:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Cc:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=MWhYFQSJflFHXKkVetnxZTBwAhr4R9h5w5CpDYF2N+A=; b=3Mhm73bypfD+09 5eVvRoYuepf74DkScw2we5pqFqqwgTq0gv77fdrU4ijpOYwW1HRZsahOcCLjGL29jflFiHuwm6dKh GQzAoeHZ6E9IPv7kkrZybZ012ouQWsb3eaWqkK6B9eu5uDR3Tn97nbdlHjjfuNvfcCihZ1DPUSJ3n xFuWGmebfyV3WMpJBiBoukMe0NTIf3zRWJUJoBdVWCg44/guHJO/+JWLXYLxkgsIW9FEYZQIVpj7k 31maikJ+UnY4+7wNLyS4PKUuRsa9IUntpgwVFUPf91hffVNC6B9nOWyN9neclYTWgHo0Utrmvzl2n rWxLanLYPhwno57xx6bw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rUNve-0000000C0vp-2YGm; Mon, 29 Jan 2024 09:27:46 +0000 Received: from 60-248-80-70.hinet-ip.hinet.net ([60.248.80.70] helo=Atcsqr.andestech.com) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rUNvM-0000000C0ij-2Q1s; Mon, 29 Jan 2024 09:27:31 +0000 Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 40T9QPvi080151; Mon, 29 Jan 2024 17:26:25 +0800 (+08) (envelope-from peterlin@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Mon, 29 Jan 2024 17:26:21 +0800 From: Yu Chien Peter Lin To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v8 05/10] riscv: dts: renesas: r9a07g043f: Update compatible string to use Andes INTC Date: Mon, 29 Jan 2024 17:25:48 +0800 Message-ID: <20240129092553.2058043-6-peterlin@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240129092553.2058043-1-peterlin@andestech.com> References: <20240129092553.2058043-1-peterlin@andestech.com> MIME-Version: 1.0 X-Originating-IP: [10.0.15.183] X-DNSRBL: X-MAIL: Atcsqr.andestech.com 40T9QPvi080151 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240129_012729_192924_9A19B125 X-CRM114-Status: UNSURE ( 8.71 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The Andes hart-level interrupt controller (Andes INTC) allows AX45MP cores to handle custom local interrupts, such as the performance counter overflow interrupt. Signed-off-by: Yu Chien Peter Lin Reviewed-by: Geert Uytterhoeven Reviewed-by: Lad Prabhakar Tested-by: Lad Prabhakar --- Changes v1 -> v2: - New patch Changes v2 -> v3: - Fixed possible compatibles for Andes INTC Changes v3 -> v4: - No change Changes v4 -> v5: - Include Geert's Reviewed-by - Include Prabhakar's Reviewed/Tested-by Changes v5 -> v6: - No change Changes v6 -> v7: - No change Changes v7 -> v8: - No change --- arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi index a92cfcfc021b..099f3df75b42 100644 --- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi @@ -39,7 +39,7 @@ cpu0: cpu@0 { cpu0_intc: interrupt-controller { #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; + compatible = "andestech,cpu-intc", "riscv,cpu-intc"; interrupt-controller; }; };