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Wed, 31 Jan 2024 22:40:45 -0800 (PST) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id y9-20020aa79e09000000b006ddc7af02c1sm10925764pfq.9.2024.01.31.22.40.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 Jan 2024 22:40:45 -0800 (PST) From: Charlie Jenkins Date: Wed, 31 Jan 2024 22:40:22 -0800 Subject: [PATCH 1/2] riscv: lib: Introduce has_fast_misaligned_access function MIME-Version: 1.0 Message-Id: <20240131-disable_misaligned_probe_config-v1-1-98d155e9cda8@rivosinc.com> References: <20240131-disable_misaligned_probe_config-v1-0-98d155e9cda8@rivosinc.com> In-Reply-To: <20240131-disable_misaligned_probe_config-v1-0-98d155e9cda8@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Jisheng Zhang , Evan Green Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Charlie Jenkins X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1706769643; l=1864; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; 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X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Create has_fast_misaligned_access to avoid needing to explicitly check the fast_misaligned_access_speed_key static key. Signed-off-by: Charlie Jenkins --- arch/riscv/include/asm/cpufeature.h | 6 ++++++ arch/riscv/lib/csum.c | 5 +---- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h index 5a626ed2c47a..dfdcca229174 100644 --- a/arch/riscv/include/asm/cpufeature.h +++ b/arch/riscv/include/asm/cpufeature.h @@ -28,7 +28,9 @@ struct riscv_isainfo { DECLARE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo); +#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS DECLARE_PER_CPU(long, misaligned_access_speed); +#endif /* Per-cpu ISA extensions. */ extern struct riscv_isainfo hart_isa[NR_CPUS]; @@ -137,4 +139,8 @@ static __always_inline bool riscv_cpu_has_extension_unlikely(int cpu, const unsi DECLARE_STATIC_KEY_FALSE(fast_misaligned_access_speed_key); +static __always_inline bool has_fast_misaligned_accesses(void) +{ + return static_branch_likely(&fast_misaligned_access_speed_key); +} #endif diff --git a/arch/riscv/lib/csum.c b/arch/riscv/lib/csum.c index af3df5274ccb..399fa09bf4cb 100644 --- a/arch/riscv/lib/csum.c +++ b/arch/riscv/lib/csum.c @@ -318,10 +318,7 @@ unsigned int do_csum(const unsigned char *buff, int len) * branches. The largest chunk of overlap was delegated into the * do_csum_common function. */ - if (static_branch_likely(&fast_misaligned_access_speed_key)) - return do_csum_no_alignment(buff, len); - - if (((unsigned long)buff & OFFSET_MASK) == 0) + if (has_fast_misaligned_accesses() || (((unsigned long)buff & OFFSET_MASK) == 0b101)) return do_csum_no_alignment(buff, len); return do_csum_with_alignment(buff, len);