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Mon, 12 Feb 2024 19:37:48 -0800 (PST) X-Forwarded-Encrypted: i=1; AJvYcCUtDxXelkbmm+CM8OLoo8WM4giaZcxrKGw5FC1up94u0V6jYFdJloVUPvWRQ0Omxq/n9YRlGpQXAYGpmEIR7+klWd8162GgnV8tbjfr9NG9RNhsxttq1+vCK9foEoC0wKl6LWJ+VJ9OhaR6eZRwNvpqxF3p8xEUSYrb8ksnc2H07sCCYQfJvwH5l0u3YCp2Z9mi1xR2N69GDslZW7YF Received: from sw06.internal.sifive.com ([4.53.31.132]) by smtp.gmail.com with ESMTPSA id v11-20020a056a00148b00b006e0334e3dd9sm6188633pfu.76.2024.02.12.19.37.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Feb 2024 19:37:47 -0800 (PST) From: Samuel Holland To: Palmer Dabbelt Cc: Andrew Jones , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Stefan O'Rear , Samuel Holland Subject: [PATCH -fixes v2 2/4] dt-bindings: riscv: Add ratified privileged ISA versions Date: Mon, 12 Feb 2024 19:37:33 -0800 Message-ID: <20240213033744.4069020-3-samuel.holland@sifive.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240213033744.4069020-1-samuel.holland@sifive.com> References: <20240213033744.4069020-1-samuel.holland@sifive.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240212_193749_258544_2FA36FDB X-CRM114-Status: UNSURE ( 9.27 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The baseline for the RISC-V privileged ISA is version 1.10. Using features from newer versions of the privileged ISA requires the supported version to be reported by platform firmware, either in the ISA string (where the binding already accepts version numbers) or in the riscv,isa-extensions property. So far two newer versions are ratified. Signed-off-by: Samuel Holland Reviewed-by: Andrew Jones --- Changes in v2: - New patch for v2 .../devicetree/bindings/riscv/extensions.yaml | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index 63d81dc895e5..7faf22df01af 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -121,6 +121,16 @@ properties: version of the privileged ISA specification. # multi-letter extensions, sorted alphanumerically + - const: sm1p11 + description: + The standard Machine ISA v1.11, as ratified in the 20190608 + version of the privileged ISA specification. + + - const: sm1p12 + description: + The standard Machine ISA v1.12, as ratified in the 20211203 + version of the privileged ISA specification. + - const: smaia description: | The standard Smaia supervisor-level extension for the advanced @@ -134,6 +144,16 @@ properties: added by other RISC-V extensions in H/S/VS/U/VU modes and as ratified at commit a28bfae (Ratified (#7)) of riscv-state-enable. + - const: ss1p11 + description: + The standard Supervisor ISA v1.11, as ratified in the 20190608 + version of the privileged ISA specification. + + - const: ss1p12 + description: + The standard Supervisor ISA v1.12, as ratified in the 20211203 + version of the privileged ISA specification. + - const: ssaia description: | The standard Ssaia supervisor-level extension for the advanced