From patchwork Tue Feb 13 22:39:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eric Chan X-Patchwork-Id: 13555806 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A3122C48260 for ; Tue, 13 Feb 2024 22:39:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:Message-ID: References:Mime-Version:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=Wfhau4lNy2cAl3EGf77+Hf+ilhxK4tjJQtenUD7aXls=; b=FkU2zD6eE4KWkSnyJff6/ysU6x w+W+vaWgot05Sr4Rif0UxQxPZxp8iS1dFV4VQZBAAkW8Uojuvk0crs6PkuDeuYm99q+BmWrdU5xhd Y6ijav4Dpx+vWLNHLnnNDrPVxpSTLyMG9+Iw85PK1lzSNu100DCPqeDt4Mo93tNz+LYvu+XwFjPL5 wMGfpGPearrtdpr3ZHo3GnH4QHHfUqFwTqxqGHoa39IwaYOgMHsLQc+LeBeHlvmDRWalyARDNffOi VXzx/MvpZDzBQ8udKEoZev72uG9g1F+/6tz5+PVR1LhG2yLt7Bpk4Hu/OsFvTPNZnMIl9va4iYIN6 zqNIF8Xw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1ra1R6-0000000B6c5-2PAd; Tue, 13 Feb 2024 22:39:32 +0000 Received: from mail-yw1-x1149.google.com ([2607:f8b0:4864:20::1149]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1ra1R4-0000000B6b3-3Lvx for linux-riscv@lists.infradead.org; Tue, 13 Feb 2024 22:39:32 +0000 Received: by mail-yw1-x1149.google.com with SMTP id 00721157ae682-5ffee6fcdc1so78635377b3.2 for ; Tue, 13 Feb 2024 14:39:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1707863969; x=1708468769; darn=lists.infradead.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=2A5s0YU98xz4fK0cK8V3de3MUudesnEU1GM23Fa1guU=; b=Dbal9Evv76jUvUAt89nxCNFBuwaxglrQOw2QegTb2aEt76RlNlu9Pos43j267aVu2A 90+7ywlHTdPFAEJozIRZadaq1+2+R0nRn+XuLUMpudyUDXqPdX+EL1H3L6FfCFRWpZis IZJDIsUcQWfGJEfI+MeP2sTvRlUOaaP6A+L2hLaLBdFHrbbi9NorFXD/rFIyuH1ZEmNG RwBxED5Q0TdJGlaStGp8C3Vc4PlM7PTRZmUrjtV+XwLXKwltpftKt7W2K7PE7awHYQb3 kpBUcqhDkhYieo26WfWSt7i343lhvmc51wre95GHUooywoJU+l0bxyEh4PGS6Xpr/gwa R4Ug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1707863969; x=1708468769; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=2A5s0YU98xz4fK0cK8V3de3MUudesnEU1GM23Fa1guU=; b=GpbM0REnTBYlKuwgY34bfnCw3/fDU2IE7+DnvJzI8fyapBRjOSEbLnUateBGyEqSNo 6VyXSvgj++/r4/70R9xedZuQ3brH/Cvd8Nb1DUTO+/J1cXxte7We9S22+lyj1p7DQ3O8 0dRgYkMLCiFywSWI/B1OgpfIWarn1AUwg/vBw0MpANHao8nRsYpkvYvWiNzJUQlmtGqK NSMvV3i38UslM65Q2DWjUR/AKBHBJv5LwCpU6Cj1mnj+vc+NoK2sa8yRk2cbRdRj4VA/ bmxfn08F4QFxQIvxED1x/bUZmdIBhnokXuzNY/x2Cl45D2F7fchBDnxJBxUSQVWmoyif JjRg== X-Gm-Message-State: AOJu0YxG3+3osIkmKGi+38AgtdG1/UP9+Iy9ZzLjLEx9FgL/Z5aCD/F8 3kU03Lntn+XFa1OmxCuRqrxk9RhLyk5nS/8V9z0gbXjA8FhnTIPEvwtTt9OvrJzgwYDQkWpqLgq T1HbMFEH9lV5o24HkVg== X-Google-Smtp-Source: AGHT+IEIi+wYTmQJyxcKODqt/e4zjlJ+9u4VEaVmzXIRBnTsS/drWHfQ9rn0ZFxxYlAcorE8rSRQo+ev1twJewgu X-Received: from ericchancf.c.googlers.com ([fda3:e722:ac3:cc00:4f:4b78:c0a8:4139]) (user=ericchancf job=sendgmr) by 2002:a05:6902:1027:b0:dc6:dd76:34cc with SMTP id x7-20020a056902102700b00dc6dd7634ccmr45468ybt.1.1707863969224; Tue, 13 Feb 2024 14:39:29 -0800 (PST) Date: Tue, 13 Feb 2024 22:39:23 +0000 In-Reply-To: <20240213223810.2595804-1-ericchancf@google.com> Mime-Version: 1.0 References: <20240213223810.2595804-1-ericchancf@google.com> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog Message-ID: <20240213223923.2597036-1-ericchancf@google.com> Subject: [PATCH v5 2/4] riscv/barrier: Define RISCV_FULL_BARRIER From: Eric Chan To: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, ericchancf@google.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240213_143930_851960_D2CDF23D X-CRM114-Status: UNSURE ( 8.72 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Introduce RISCV_FULL_BARRIER and use in arch_atomic* function. like RISCV_ACQUIRE_BARRIER and RISCV_RELEASE_BARRIER, the fence instruction can be eliminated When SMP is not enabled. Signed-off-by: Eric Chan --- arch/riscv/include/asm/atomic.h | 16 ++++++++-------- arch/riscv/include/asm/cmpxchg.h | 4 ++-- arch/riscv/include/asm/fence.h | 2 ++ 3 files changed, 12 insertions(+), 10 deletions(-) diff --git a/arch/riscv/include/asm/atomic.h b/arch/riscv/include/asm/atomic.h index f5dfef6c2153..31e6e2e7cc18 100644 --- a/arch/riscv/include/asm/atomic.h +++ b/arch/riscv/include/asm/atomic.h @@ -207,7 +207,7 @@ static __always_inline int arch_atomic_fetch_add_unless(atomic_t *v, int a, int " add %[rc], %[p], %[a]\n" " sc.w.rl %[rc], %[rc], %[c]\n" " bnez %[rc], 0b\n" - " fence rw, rw\n" + RISCV_FULL_BARRIER "1:\n" : [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter) : [a]"r" (a), [u]"r" (u) @@ -228,7 +228,7 @@ static __always_inline s64 arch_atomic64_fetch_add_unless(atomic64_t *v, s64 a, " add %[rc], %[p], %[a]\n" " sc.d.rl %[rc], %[rc], %[c]\n" " bnez %[rc], 0b\n" - " fence rw, rw\n" + RISCV_FULL_BARRIER "1:\n" : [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter) : [a]"r" (a), [u]"r" (u) @@ -248,7 +248,7 @@ static __always_inline bool arch_atomic_inc_unless_negative(atomic_t *v) " addi %[rc], %[p], 1\n" " sc.w.rl %[rc], %[rc], %[c]\n" " bnez %[rc], 0b\n" - " fence rw, rw\n" + RISCV_FULL_BARRIER "1:\n" : [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter) : @@ -268,7 +268,7 @@ static __always_inline bool arch_atomic_dec_unless_positive(atomic_t *v) " addi %[rc], %[p], -1\n" " sc.w.rl %[rc], %[rc], %[c]\n" " bnez %[rc], 0b\n" - " fence rw, rw\n" + RISCV_FULL_BARRIER "1:\n" : [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter) : @@ -288,7 +288,7 @@ static __always_inline int arch_atomic_dec_if_positive(atomic_t *v) " bltz %[rc], 1f\n" " sc.w.rl %[rc], %[rc], %[c]\n" " bnez %[rc], 0b\n" - " fence rw, rw\n" + RISCV_FULL_BARRIER "1:\n" : [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter) : @@ -310,7 +310,7 @@ static __always_inline bool arch_atomic64_inc_unless_negative(atomic64_t *v) " addi %[rc], %[p], 1\n" " sc.d.rl %[rc], %[rc], %[c]\n" " bnez %[rc], 0b\n" - " fence rw, rw\n" + RISCV_FULL_BARRIER "1:\n" : [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter) : @@ -331,7 +331,7 @@ static __always_inline bool arch_atomic64_dec_unless_positive(atomic64_t *v) " addi %[rc], %[p], -1\n" " sc.d.rl %[rc], %[rc], %[c]\n" " bnez %[rc], 0b\n" - " fence rw, rw\n" + RISCV_FULL_BARRIER "1:\n" : [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter) : @@ -352,7 +352,7 @@ static __always_inline s64 arch_atomic64_dec_if_positive(atomic64_t *v) " bltz %[rc], 1f\n" " sc.d.rl %[rc], %[rc], %[c]\n" " bnez %[rc], 0b\n" - " fence rw, rw\n" + RISCV_FULL_BARRIER "1:\n" : [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter) : diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpxchg.h index 2f4726d3cfcc..a608e4d1a0a4 100644 --- a/arch/riscv/include/asm/cmpxchg.h +++ b/arch/riscv/include/asm/cmpxchg.h @@ -313,7 +313,7 @@ " bne %0, %z3, 1f\n" \ " sc.w.rl %1, %z4, %2\n" \ " bnez %1, 0b\n" \ - " fence rw, rw\n" \ + RISCV_FULL_BARRIER \ "1:\n" \ : "=&r" (__ret), "=&r" (__rc), "+A" (*__ptr) \ : "rJ" ((long)__old), "rJ" (__new) \ @@ -325,7 +325,7 @@ " bne %0, %z3, 1f\n" \ " sc.d.rl %1, %z4, %2\n" \ " bnez %1, 0b\n" \ - " fence rw, rw\n" \ + RISCV_FULL_BARRIER \ "1:\n" \ : "=&r" (__ret), "=&r" (__rc), "+A" (*__ptr) \ : "rJ" (__old), "rJ" (__new) \ diff --git a/arch/riscv/include/asm/fence.h b/arch/riscv/include/asm/fence.h index 2b443a3a487f..6c26c44dfcd6 100644 --- a/arch/riscv/include/asm/fence.h +++ b/arch/riscv/include/asm/fence.h @@ -4,9 +4,11 @@ #ifdef CONFIG_SMP #define RISCV_ACQUIRE_BARRIER "\tfence r , rw\n" #define RISCV_RELEASE_BARRIER "\tfence rw, w\n" +#define RISCV_FULL_BARRIER "\tfence rw, rw\n" #else #define RISCV_ACQUIRE_BARRIER #define RISCV_RELEASE_BARRIER +#define RISCV_FULL_BARRIER #endif #endif /* _ASM_RISCV_FENCE_H */