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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id cv17-20020a17090afd1100b002a02f8d350fsm2628830pjb.53.2024.03.29.02.27.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Mar 2024 02:27:54 -0700 (PDT) From: Max Hsu Date: Fri, 29 Mar 2024 17:26:20 +0800 Subject: [PATCH RFC 04/11] riscv: Add Sdtrig CSRs definition, Smstateen bit to access Sdtrig CSRs MIME-Version: 1.0 Message-Id: <20240329-dev-maxh-lin-452-6-9-v1-4-1534f93b94a7@sifive.com> References: <20240329-dev-maxh-lin-452-6-9-v1-0-1534f93b94a7@sifive.com> In-Reply-To: <20240329-dev-maxh-lin-452-6-9-v1-0-1534f93b94a7@sifive.com> To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J. Wysocki" , Pavel Machek , Anup Patel , Atish Patra , Paolo Bonzini , Shuah Khan Cc: Palmer Dabbelt , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org, Max Hsu X-Mailer: b4 0.13.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240329_092757_229074_62E007F5 X-CRM114-Status: UNSURE ( 7.51 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add hcontext/scontext CSRs definition to csr.h As riscv-state-enable [1] Smstateen extension spec: Sdtrig CSRs: hcontext/scontext availability are controlled by bit 57 of Smstateen CSRs. Link: https://github.com/riscvarchive/riscv-state-enable/releases/download/v1.0.0/Smstateen.pdf [1] Signed-off-by: Max Hsu --- arch/riscv/include/asm/csr.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 2468c55933cd..308ae795dc82 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -204,6 +204,8 @@ #define ENVCFG_FIOM _AC(0x1, UL) /* Smstateen bits */ +#define SMSTATEEN0_HSCONTEXT_SHIFT 57 +#define SMSTATEEN0_HSCONTEXT (_ULL(1) << SMSTATEEN0_HSCONTEXT_SHIFT) #define SMSTATEEN0_AIA_IMSIC_SHIFT 58 #define SMSTATEEN0_AIA_IMSIC (_ULL(1) << SMSTATEEN0_AIA_IMSIC_SHIFT) #define SMSTATEEN0_AIA_SHIFT 59 @@ -480,6 +482,10 @@ #define IE_TIE (_AC(0x1, UL) << RV_IRQ_TIMER) #define IE_EIE (_AC(0x1, UL) << RV_IRQ_EXT) +/* riscv-debug-spec: Sdtrig extension */ +#define CSR_SCONTEXT 0x5a8 +#define CSR_HCONTEXT 0x6a8 + #ifndef __ASSEMBLY__ #define csr_swap(csr, val) \