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Mon, 08 Apr 2024 23:12:21 -0700 (PDT) Received: from debug.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id n3-20020a170902e54300b001e3dd5972ccsm5775564plf.185.2024.04.08.23.12.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Apr 2024 23:12:21 -0700 (PDT) From: Deepak Gupta To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev Cc: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, nathan@kernel.org, ndesaulniers@google.com, morbo@google.com, justinstitt@google.com, andy.chiu@sifive.com, debug@rivosinc.com, hankuan.chen@sifive.com, guoren@kernel.org, greentime.hu@sifive.com, samitolvanen@google.com, cleger@rivosinc.com, apatel@ventanamicro.com, ajones@ventanamicro.com, conor.dooley@microchip.com, mchitale@ventanamicro.com, dbarboza@ventanamicro.com, waylingii@gmail.com, sameo@rivosinc.com, alexghiti@rivosinc.com, akpm@linux-foundation.org, shikemeng@huaweicloud.com, rppt@kernel.org, charlie@rivosinc.com, xiao.w.wang@intel.com, willy@infradead.org, jszhang@kernel.org, leobras@redhat.com, songshuaishuai@tinylab.org, haxel@fzi.de, samuel.holland@sifive.com, namcaov@gmail.com, bjorn@rivosinc.com, cuiyunhui@bytedance.com, wangkefeng.wang@huawei.com, falcon@tinylab.org, viro@zeniv.linux.org.uk, bhe@redhat.com, chenjiahao16@huawei.com, hca@linux.ibm.com, arnd@arndb.de, kent.overstreet@linux.dev, boqun.feng@gmail.com, oleg@redhat.com, paulmck@kernel.org, broonie@kernel.org, rick.p.edgecombe@intel.com Subject: [RFC PATCH 12/12] riscv: enable kernel shadow stack and landing pad enforcement Date: Mon, 8 Apr 2024 23:10:43 -0700 Message-Id: <20240409061043.3269676-13-debug@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240409061043.3269676-1-debug@rivosinc.com> References: <20240409061043.3269676-1-debug@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240408_231224_646505_4355A0E7 X-CRM114-Status: UNSURE ( 9.29 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org This patch enables kernel shadow stack and landing pad enforcement by invoking a SBI call. As of now it just issues a SBI_EXT_BASE and a hacked up opensbi implementation sets the LPE/SSE bits in menvcfg Eventually, we should have fwft [1] interface using which kernel should be able to set this enforcement properly [1] - https://lists.riscv.org/g/tech-prs/message/833 Signed-off-by: Deepak Gupta --- arch/riscv/kernel/head.S | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S index bc248c137c90..1e5bc7b2ee75 100644 --- a/arch/riscv/kernel/head.S +++ b/arch/riscv/kernel/head.S @@ -164,6 +164,13 @@ secondary_start_sbi: call relocate_enable_mmu #endif call .Lsetup_trap_vector + /* + * Temp hack to get menvcfg.SSE=1 and menvcfg.LPE=1 by invoking + * SBI_EXT_BASE + */ + li a6, 0 + li a7, 0x10 + ecall scs_load_current t0 lui t2, 0x1 tail smp_callin @@ -313,6 +320,13 @@ SYM_CODE_START(_start_kernel) la tp, init_task la sp, init_thread_union + THREAD_SIZE addi sp, sp, -PT_SIZE_ON_STACK + /* + * Temp hack to get menvcfg.SSE=1 and menvcfg.LPE=1 by invoking + * SBI_EXT_BASE + */ + li a6, 0 + li a7, 0x10 + ecall scs_load_current t0 #ifdef CONFIG_KASAN