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AJvYcCVIz3ypu3UgJev5Kz1hgPC4cjhAV/1VsoBr5L8nRfWzQflFpPytSWcfdpATsC17R2ocsoP8jHutr/Bd2mjq4xqB/RE5lfs/F0i8OwoLrRTM X-Gm-Message-State: AOJu0YyxBZkkXdrPv30JDO6Ouia29edpzlVBYrOuV6Yo6v3pED/EB6Mc 28pfro1dD2mhvzgpO43vEOmdif5AOlNQlS8ZtedmtjF8u8R6pyt9SlXfweQ50JA= X-Google-Smtp-Source: AGHT+IEeADcSOG5m5cSI0ix14SxkbexoEWR7Z85N/k76lNUya9yj2CgCsg1obRQTztWOVlClkCQkEQ== X-Received: by 2002:a05:6808:6044:b0:3c5:fb09:aeea with SMTP id dd4-20020a056808604400b003c5fb09aeeamr11353481oib.35.1713237294624; Mon, 15 Apr 2024 20:14:54 -0700 (PDT) Received: from L6YN4KR4K9.bytedance.net ([61.213.176.12]) by smtp.gmail.com with ESMTPSA id d20-20020aa78694000000b006e6adfb8897sm7907983pfo.156.2024.04.15.20.14.49 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 15 Apr 2024 20:14:54 -0700 (PDT) From: Yunhui Cui To: rafael@kernel.org, lenb@kernel.org, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, linux-riscv@lists.infradead.org, bhelgaas@google.com, james.morse@arm.com, jhugo@codeaurora.org, jeremy.linton@arm.com, john.garry@huawei.com, Jonathan.Cameron@huawei.com, pierre.gondois@arm.com, sudeep.holla@arm.com, tiantao6@huawei.com Cc: Yunhui Cui Subject: [PATCH v3 2/3] riscv: cacheinfo: initialize cacheinfo's level and type from ACPI PPTT Date: Tue, 16 Apr 2024 11:14:37 +0800 Message-Id: <20240416031438.7637-2-cuiyunhui@bytedance.com> X-Mailer: git-send-email 2.39.2 (Apple Git-143) In-Reply-To: <20240416031438.7637-1-cuiyunhui@bytedance.com> References: <20240416031438.7637-1-cuiyunhui@bytedance.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240415_201456_977946_A357ACD8 X-CRM114-Status: GOOD ( 11.38 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Before cacheinfo can be built correctly, we need to initialize level and type. Since RSIC-V currently does not have a register group that describes cache-related attributes like ARM64, we cannot obtain them directly, so now we obtain cache leaves from the ACPI PPTT table (acpi_get_cache_info()) and set the cache type through split_levels. Suggested-by: Jeremy Linton Suggested-by: Sudeep Holla Signed-off-by: Yunhui Cui Reviewed-by: Sudeep Holla --- arch/riscv/kernel/cacheinfo.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/riscv/kernel/cacheinfo.c b/arch/riscv/kernel/cacheinfo.c index 30a6878287ad..dc5fb70362f1 100644 --- a/arch/riscv/kernel/cacheinfo.c +++ b/arch/riscv/kernel/cacheinfo.c @@ -6,6 +6,7 @@ #include #include #include +#include static struct riscv_cacheinfo_ops *rv_cache_ops; @@ -78,6 +79,25 @@ int populate_cache_leaves(unsigned int cpu) struct device_node *prev = NULL; int levels = 1, level = 1; + if (!acpi_disabled) { + int ret, idx, fw_levels, split_levels; + + ret = acpi_get_cache_info(cpu, &fw_levels, &split_levels); + if (ret) + return ret; + + for (idx = 0; level <= this_cpu_ci->num_levels && + idx < this_cpu_ci->num_leaves; idx++, level++) { + if (level <= split_levels) { + ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level); + ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level); + } else { + ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level); + } + } + return 0; + } + if (of_property_read_bool(np, "cache-size")) ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level); if (of_property_read_bool(np, "i-cache-size"))