From patchwork Thu Apr 18 14:21:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 13634918 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 81654C4345F for ; Thu, 18 Apr 2024 14:21:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=sfAzPrjbXyrcz7G2jLrjRkJGn+dCTqE+LiSfqg/X3TM=; b=klT2KrizKFt9f/ 2FcvCLlUkKXgT46Qkm1sFtk5w0EHdRZLRro85eU/xPGU6cq7wT67SEsNS7RJmU/MSuj2wS8e29FgO I5Ml+493yyCp9wR66UkjBiW6GlhhqaaA1lBGeZu1HT5w6EtB29ijYE7N26HwBANr0JtE5LZrtclwJ 5vYysGPBneLErTF9KFl91QNZoJw8cFZAPyLN/Er10xTCOgETH7wIWlNUkmhURLuN3ze4O5nxxH17Y 8rLHKYdPj4A21D/QAQQnD1evWPTA40+USeDKJ6reCBxQ0DcpD5jqf0GqCycfFl9aABkbTI112HWBK jTHeSWAvHsAtoaTcEGFA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rxSdv-00000002auw-370L; Thu, 18 Apr 2024 14:21:39 +0000 Received: from sin.source.kernel.org ([2604:1380:40e1:4800::1]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rxSds-00000002asp-1GL2 for linux-riscv@lists.infradead.org; Thu, 18 Apr 2024 14:21:38 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sin.source.kernel.org (Postfix) with ESMTP id 449FBCE162B; Thu, 18 Apr 2024 14:21:34 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3BF75C113CC; Thu, 18 Apr 2024 14:21:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1713450092; bh=aUM0Xf17pxFUy6Cr+9PH1jkH+tLH18RFiiZ8wiEHNyg=; h=From:To:Cc:Subject:Date:From; b=OOtcW97s6gnerm+tffJItV7ew9zy1ZhSrvMo02RgX0ZKyCqH6YI5v/LvsHbYyrfBB gHtxJJeMGexhCWow0EK+VYT+ar3LU591BkU1ndoautpWZxkuXlKYO6a6BUSZR8nLNY POIswoimSwvsP6a5nlfoLxsakWhfbzrnOwBitY9ssyuNsPEuDltVnVxtvuI/hMq76N vG/Uog8auWPLN8QpGxPIG7zFvcyW2UetfjQrfTYAWTtqll7jYLh/vxxM/BWCRXH8p3 zonPVmBcl85quvEQ/cXPfaZpLHhOE3Qz1qUPbCkp1E8hTUmM/IomwlLI8XYgv/u34w RXKqNFZFD87wA== From: Conor Dooley To: linux-riscv@lists.infradead.org Cc: conor@kernel.org, Conor Dooley , =?utf-8?b?QmrDtnJuIFTDtnBlbA==?= , Samuel Holland , Pu Lehui , =?utf-8?b?QmrDtnJuIFTDtnBlbA==?= , Paul Walmsley , Palmer Dabbelt , linux-kernel@vger.kernel.org Subject: [PATCH v1] RISC-V: clarify what some RISCV_ISA* config options do Date: Thu, 18 Apr 2024 15:21:01 +0100 Message-ID: <20240418-stable-railway-7cce07e1e440@spud> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=4357; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=mdQDYpXoXxz/xowCTUoQTmMv0Y172vMgP0KsAfRXkKE=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDGmKOj7ijzraWDadNrNUnVy24Kh8zi7FjO0bDi6oktvrm 1VoIn+wo5SFQYyDQVZMkSXxdl+L1Po/Ljuce97CzGFlAhnCwMUpABN5rMrwP41vk132s/6tRlWP jm7l3xzx+OFFI/PLlVKaTpwHQ/jvHmNk+KKwUNf42umu6KN3PkjVHz4RkOm/J42Ro/B5Q/jHCXW XuQE= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240418_072136_735352_1035C062 X-CRM114-Status: GOOD ( 15.77 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Conor Dooley During some discussion on IRC yesterday and on Pu's bpf patch [1] I noticed that these RISCV_ISA* Kconfig options are not really clear about their implications. Many of these options have no impact on what userspace is allowed to do, for example an application can use Zbb regardless of whether or not the kernel does. Change the help text to try and clarify whether or not an option affects just the kernel, or also userspace. None of these options actually control whether or not an extension is detected dynamically as that's done regardless of Kconfig options, so drop any text that implies the option is required for dynamic detection, rewording them as "do x when y is detected". Link: https://lore.kernel.org/linux-riscv/20240328-ferocity-repose-c554f75a676c@spud/ [1] Reviewed-by: Björn Töpel Signed-off-by: Conor Dooley Reviewed-by: Samuel Holland --- Vector copy-paste-o fixed, correct spelling of optimisations kept. CC: Samuel Holland CC: Pu Lehui CC: Björn Töpel CC: Paul Walmsley CC: Palmer Dabbelt CC: linux-riscv@lists.infradead.org CC: linux-kernel@vger.kernel.org --- arch/riscv/Kconfig | 28 +++++++++++++++------------- 1 file changed, 15 insertions(+), 13 deletions(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 6d64888134ba..c3a7793b0a7c 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -503,8 +503,8 @@ config RISCV_ISA_SVNAPOT depends on RISCV_ALTERNATIVE default y help - Allow kernel to detect the Svnapot ISA-extension dynamically at boot - time and enable its usage. + Add support for the Svnapot ISA-extension when it is detected by + the kernel at boot. The Svnapot extension is used to mark contiguous PTEs as a range of contiguous virtual-to-physical translations for a naturally @@ -522,9 +522,9 @@ config RISCV_ISA_SVPBMT depends on RISCV_ALTERNATIVE default y help - Adds support to dynamically detect the presence of the Svpbmt - ISA-extension (Supervisor-mode: page-based memory types) and - enable its usage. + Add support for the Svpbmt ISA-extension (Supervisor-mode: + page-based memory types) when it is detected by the kernel at + boot. The memory type for a page contains a combination of attributes that indicate the cacheability, idempotency, and ordering @@ -543,14 +543,15 @@ config TOOLCHAIN_HAS_V depends on AS_HAS_OPTION_ARCH config RISCV_ISA_V - bool "VECTOR extension support" + bool "Vector extension support" depends on TOOLCHAIN_HAS_V depends on FPU select DYNAMIC_SIGFRAME default y help Say N here if you want to disable all vector related procedure - in the kernel. + in the kernel. Without this option enabled, neither the kernel nor + userspace may use vector. If you don't know what to do here, say Y. @@ -608,8 +609,8 @@ config RISCV_ISA_ZBB depends on RISCV_ALTERNATIVE default y help - Adds support to dynamically detect the presence of the ZBB - extension (basic bit manipulation) and enable its usage. + Add support for enabling optimisations in the kernel when the + Zbb extension is detected at boot. The Zbb extension provides instructions to accelerate a number of bit-specific operations (count bit population, sign extending, @@ -625,9 +626,9 @@ config RISCV_ISA_ZICBOM select RISCV_DMA_NONCOHERENT select DMA_DIRECT_REMAP help - Adds support to dynamically detect the presence of the ZICBOM - extension (Cache Block Management Operations) and enable its - usage. + Add support for the Zicbom extension (Cache Block Management + Operations) and enable its use in the kernel when it is detected + at boot. The Zicbom extension can be used to handle for example non-coherent DMA support on devices that need it. @@ -686,7 +687,8 @@ config FPU default y help Say N here if you want to disable all floating-point related procedure - in the kernel. + in the kernel. Without this option enabled, neither the kernel nor + userspace may use floating-point procedures. If you don't know what to do here, say Y.