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Signed-off-by: Alex Soo --- drivers/pinctrl/starfive/Kconfig | 12 ++ drivers/pinctrl/starfive/Makefile | 1 + .../pinctrl-starfive-jh8100-sys-west.c | 164 ++++++++++++++++++ .../starfive/pinctrl-starfive-jh8100.c | 6 + .../starfive/pinctrl-starfive-jh8100.h | 5 + 5 files changed, 188 insertions(+) create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive-jh8100-sys-west.c diff --git a/drivers/pinctrl/starfive/Kconfig b/drivers/pinctrl/starfive/Kconfig index afcbf9d4dc8d..d78f161a636c 100644 --- a/drivers/pinctrl/starfive/Kconfig +++ b/drivers/pinctrl/starfive/Kconfig @@ -70,3 +70,15 @@ config PINCTRL_STARFIVE_JH8100_SYS_EAST This also provides an interface to the GPIO pins not used by other peripherals supporting inputs, outputs, configuring pull-up/pull-down and interrupts on input changes. + +config PINCTRL_STARFIVE_JH8100_SYS_WEST + tristate "StarFive JH8100 SoC System IOMUX-West pinctrl and GPIO driver" + depends on ARCH_STARFIVE || COMPILE_TEST + depends on OF + select PINCTRL_STARFIVE_JH8100 + default ARCH_STARFIVE + help + Say yes here to support system iomux-west pin control on the StarFive JH8100 SoC. + This also provides an interface to the GPIO pins not used by other + peripherals supporting inputs, outputs, configuring pull-up/pull-down + and interrupts on input changes. diff --git a/drivers/pinctrl/starfive/Makefile b/drivers/pinctrl/starfive/Makefile index 45698c502b48..784465157ae2 100644 --- a/drivers/pinctrl/starfive/Makefile +++ b/drivers/pinctrl/starfive/Makefile @@ -8,3 +8,4 @@ obj-$(CONFIG_PINCTRL_STARFIVE_JH7110_AON) += pinctrl-starfive-jh7110-aon.o obj-$(CONFIG_PINCTRL_STARFIVE_JH8100) += pinctrl-starfive-jh8100.o obj-$(CONFIG_PINCTRL_STARFIVE_JH8100_SYS_EAST) += pinctrl-starfive-jh8100-sys-east.o +obj-$(CONFIG_PINCTRL_STARFIVE_JH8100_SYS_WEST) += pinctrl-starfive-jh8100-sys-west.o diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jh8100-sys-west.c b/drivers/pinctrl/starfive/pinctrl-starfive-jh8100-sys-west.c new file mode 100644 index 000000000000..b97d89777aa3 --- /dev/null +++ b/drivers/pinctrl/starfive/pinctrl-starfive-jh8100-sys-west.c @@ -0,0 +1,164 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Pinctrl / GPIO driver for StarFive JH8100 SoC sys west controller + * + * Copyright (C) 2023-2024 StarFive Technology Co., Ltd. + * Author: Alex Soo + * + */ + +#include +#include +#include +#include +#include + +#include + +#include "pinctrl-starfive-jh8100.h" + +#define JH8100_SYS_W_GC_BASE 0 + +/* registers */ +#define JH8100_SYS_W_DOEN 0x000 +#define JH8100_SYS_W_DOUT 0x010 +#define JH8100_SYS_W_GPI 0x020 +#define JH8100_SYS_W_GPIOIN 0x068 + +#define JH8100_SYS_W_GPIOEN 0x048 +#define JH8100_SYS_W_GPIOIS0 0x04c +#define JH8100_SYS_W_GPIOIC0 0x050 +#define JH8100_SYS_W_GPIOIBE0 0x054 +#define JH8100_SYS_W_GPIOIEV0 0x058 +#define JH8100_SYS_W_GPIOIE0 0x05c +#define JH8100_SYS_W_GPIORIS0 0x060 +#define JH8100_SYS_W_GPIOMIS0 0x064 + +static const struct pinctrl_pin_desc jh8100_sys_w_pins[] = { + PINCTRL_PIN(0, "SYS_W_GPIO0"), + PINCTRL_PIN(1, "SYS_W_GPIO1"), + PINCTRL_PIN(2, "SYS_W_GPIO2"), + PINCTRL_PIN(3, "SYS_W_GPIO3"), + PINCTRL_PIN(4, "SYS_W_GPIO4"), + PINCTRL_PIN(5, "SYS_W_GPIO5"), + PINCTRL_PIN(6, "SYS_W_GPIO6"), + PINCTRL_PIN(7, "SYS_W_GPIO7"), + PINCTRL_PIN(8, "SYS_W_GPIO8"), + PINCTRL_PIN(9, "SYS_W_GPIO9"), + PINCTRL_PIN(10, "SYS_W_GPIO10"), + PINCTRL_PIN(11, "SYS_W_GPIO11"), + PINCTRL_PIN(12, "SYS_W_GPIO12"), + PINCTRL_PIN(13, "SYS_W_GPIO13"), + PINCTRL_PIN(14, "SYS_W_GPIO14"), + PINCTRL_PIN(15, "SYS_W_GPIO15"), +}; + +static const struct jh8100_gpio_func_sel + jh8100_sys_w_func_sel[ARRAY_SIZE(jh8100_sys_w_pins)] = { + [0] = { 0xb4, 0, 2 }, + [1] = { 0xb4, 12, 2 }, + [2] = { 0xb4, 14, 2 }, + [3] = { 0xb4, 16, 2 }, + [4] = { 0xb4, 18, 2 }, + [5] = { 0xb4, 20, 2 }, + [6] = { 0xb4, 22, 2 }, + [7] = { 0xb4, 24, 2 }, + [8] = { 0xb4, 26, 2 }, + [9] = { 0xb4, 28, 2 }, + [10] = { 0xb4, 2, 2 }, + [11] = { 0xb4, 4, 2 }, + [12] = { 0xb4, 6, 2 }, + [13] = { 0xb4, 8, 2 }, + [14] = { 0xb4, 10, 2 }, +}; + +#ifdef CONFIG_PM_SLEEP +static int jh8100_sys_w_pinctrl_suspend(struct device *dev) +{ + struct jh8100_pinctrl *sfp; + int i; + + sfp = dev_get_drvdata(dev); + if (!sfp) + return -EINVAL; + + for (i = 0; i < sfp->info->nregs; i++) + sfp->jh8100_sys_west_regs[i] = readl_relaxed(sfp->base + (i * 4)); + + return pinctrl_force_sleep(sfp->pctl); +} + +static int jh8100_sys_w_pinctrl_resume(struct device *dev) +{ + struct jh8100_pinctrl *sfp; + int i; + + sfp = dev_get_drvdata(dev); + if (!sfp) + return -EINVAL; + + for (i = 0; i < sfp->info->nregs; i++) + writel_relaxed(sfp->jh8100_sys_west_regs[i], sfp->base + (i * 4)); + + return pinctrl_force_default(sfp->pctl); +} +#endif + +static SIMPLE_DEV_PM_OPS(jh8100_sys_w_pinctrl_dev_pm_ops, + jh8100_sys_w_pinctrl_suspend, + jh8100_sys_w_pinctrl_resume); + +static const struct jh8100_gpio_irq_reg jh8100_sys_w_irq_reg = { + .is_reg_base = JH8100_SYS_W_GPIOIS0, + .ic_reg_base = JH8100_SYS_W_GPIOIC0, + .ibe_reg_base = JH8100_SYS_W_GPIOIBE0, + .iev_reg_base = JH8100_SYS_W_GPIOIEV0, + .ie_reg_base = JH8100_SYS_W_GPIOIE0, + .ris_reg_base = JH8100_SYS_W_GPIORIS0, + .mis_reg_base = JH8100_SYS_W_GPIOMIS0, + .ien_reg_base = JH8100_SYS_W_GPIOEN, +}; + +static const struct jh8100_pinctrl_domain_info jh8100_sys_w_pinctrl_info = { + .pins = jh8100_sys_w_pins, + .npins = ARRAY_SIZE(jh8100_sys_w_pins), + .ngpios = JH8100_SYS_W_NGPIO, + .gc_base = JH8100_SYS_W_GC_BASE, + .name = JH8100_SYS_W_DOMAIN_NAME, + .nregs = JH8100_SYS_W_REG_NUM, + .dout_reg_base = JH8100_SYS_W_DOUT, + .dout_mask = GENMASK(5, 0), + .doen_reg_base = JH8100_SYS_W_DOEN, + .doen_mask = GENMASK(4, 0), + .gpi_reg_base = JH8100_SYS_W_GPI, + .gpi_mask = GENMASK(4, 0), + .gpioin_reg_base = JH8100_SYS_W_GPIOIN, + .func_sel = jh8100_sys_w_func_sel, + .irq_reg = &jh8100_sys_w_irq_reg, + .mis_pin_num = JH8100_SYS_W_NGPIO, +}; + +static const struct of_device_id jh8100_sys_w_pinctrl_of_match[] = { + { + .compatible = "starfive,jh8100-sys-pinctrl-west", + .data = &jh8100_sys_w_pinctrl_info, + }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, jh8100_sys_w_pinctrl_of_match); + +static struct platform_driver jh8100_sys_w_pinctrl_driver = { + .probe = jh8100_pinctrl_probe, + .driver = { + .name = "starfive-jh8100-sys-pinctrl-west", +#ifdef CONFIG_PM_SLEEP + .pm = &jh8100_sys_w_pinctrl_dev_pm_ops, +#endif + .of_match_table = jh8100_sys_w_pinctrl_of_match, + }, +}; +module_platform_driver(jh8100_sys_w_pinctrl_driver); + +MODULE_DESCRIPTION("Pinctrl driver for StarFive JH8100 SoC sys west controller"); +MODULE_AUTHOR("Alex Soo "); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jh8100.c b/drivers/pinctrl/starfive/pinctrl-starfive-jh8100.c index 4b68463ff5a5..8c3e4a90d68d 100644 --- a/drivers/pinctrl/starfive/pinctrl-starfive-jh8100.c +++ b/drivers/pinctrl/starfive/pinctrl-starfive-jh8100.c @@ -333,6 +333,9 @@ static int jh8100_set_one_pin_mux(struct jh8100_pinctrl *sfp, if (!strcmp(sfp->info->name, JH8100_SYS_E_DOMAIN_NAME) && pin < sfp->gc.ngpio && func == 1) jh8100_set_function(sfp, pin, func); + else if (!strcmp(sfp->info->name, JH8100_SYS_W_DOMAIN_NAME) && + pin < sfp->gc.ngpio - 1 && func == 2) + jh8100_set_function(sfp, pin, func); return 0; } @@ -410,6 +413,9 @@ static int jh8100_get_padcfg_base(struct jh8100_pinctrl *sfp, if (!strcmp(sfp->info->name, JH8100_SYS_E_DOMAIN_NAME)) { if (pin < JH8100_SYS_E_NGPIO) return JH8100_SYS_E_GPO_PDA_00_47_CFG; + } else if (!strcmp(sfp->info->name, JH8100_SYS_W_DOMAIN_NAME)) { + if (pin < JH8100_SYS_W_NGPIO) + return JH8100_SYS_W_GPO_PDA_00_15_CFG; } return -ENXIO; diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jh8100.h b/drivers/pinctrl/starfive/pinctrl-starfive-jh8100.h index 6eb4f1896a90..7c7a05c1c828 100644 --- a/drivers/pinctrl/starfive/pinctrl-starfive-jh8100.h +++ b/drivers/pinctrl/starfive/pinctrl-starfive-jh8100.h @@ -12,12 +12,16 @@ #include "../core.h" +#define JH8100_SYS_W_DOMAIN_NAME "jh8100-sys-west" #define JH8100_SYS_E_DOMAIN_NAME "jh8100-sys-east" +#define JH8100_SYS_W_NGPIO 16 #define JH8100_SYS_E_NGPIO 48 +#define JH8100_SYS_W_REG_NUM 44 #define JH8100_SYS_E_REG_NUM 116 +#define JH8100_SYS_W_GPO_PDA_00_15_CFG 0x074 #define JH8100_SYS_E_GPO_PDA_00_47_CFG 0x114 struct jh8100_pinctrl { @@ -30,6 +34,7 @@ struct jh8100_pinctrl { /* register read/write mutex */ struct mutex mutex; const struct jh8100_pinctrl_domain_info *info; + unsigned int jh8100_sys_west_regs[JH8100_SYS_W_REG_NUM]; unsigned int jh8100_sys_east_regs[JH8100_SYS_E_REG_NUM]; /* wakeup */ struct irq_domain *irq_domain;