From patchwork Mon Jun 10 12:18:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daire McNamara X-Patchwork-Id: 13691959 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2D231C27C5E for ; Mon, 10 Jun 2024 12:19:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=u4qcYcRNgSkpjXx9Z0m7FGJW/OY+Lv1FfsvZpcrarnQ=; b=Nga+362a6m0ZRc w01RkH4U0+urvpZGEL0uD0VWBZg4Sxlv0kF3yei/aNky9zpfnKRKTSioiDzprBEjGAEWjBRSGgIKf BAT6Q6GtFmvH5n0WdN2V01XkfowCYKHz6MCOovzqvkb7R8j6cNOdPTIh5MHwYC3RyQeid7sQn89u0 BvEvEpKVzvpbf1wDAcUqJOKcJV9KfxI6tYIQGqBJOkHaEmzxo4Q0qiVclsnKC0Y8nVQzIbuPWZlaQ bo+SS1xbcYZj/DXfcaHHsPPL2oT6z90IXdi7zyG8YAKcY3AGvM3lhIq0/MIFegi1V9Ycm1ifYaYSw aPq+K1bsb0FpVc57I9wQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sGdzu-00000004ycx-1MPq; Mon, 10 Jun 2024 12:19:38 +0000 Received: from esa.microchip.iphmx.com ([68.232.153.233]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sGdzr-00000004ybC-1gcw for linux-riscv@lists.infradead.org; Mon, 10 Jun 2024 12:19:36 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1718021976; x=1749557976; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=oFdeEmSZCx2CmTI24Mlau+qRlUsKvxGoVQk9WMKPt7Y=; b=q9TxrXsdQS4wqgOG3lGZsV25Xxhx2HF7fs9eoJjrM1ehSoGF6zn0C9Il jFEpSkDyn9grVxar/zSsMsXRSEWDgnvBWqWCBuEJTSd+nDJS756Ls/jR1 X7r+D6+0yWk6v/DZquGmnxh7153+CKH9EpBsNShiqjQgZQhNRzHl8etWY Zv+gVMn1iSKkImLv4QvTXJef+5ocVjt5khT3Ubu2kzcCc9xHpyDDGTd1V dGETWRZTiugGV0HH48u39b30IvfGdGzR+V/kR4CnnqPAV1YLKLxjBkW+6 /JTNbbumnXVskUC/6J9r5k80lcdfvAlvvGJCCEVaX2xlhbWggmt284TsB Q==; X-CSE-ConnectionGUID: dqLk+HR7SaOyO/C4oxTk7g== X-CSE-MsgGUID: yGdRtAjnRVyfbWIIvRK/bg== X-IronPort-AV: E=Sophos;i="6.08,227,1712646000"; d="scan'208";a="27206508" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 10 Jun 2024 05:19:34 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 10 Jun 2024 05:18:28 -0700 Received: from daire-X570.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 10 Jun 2024 05:18:26 -0700 From: To: CC: , , , , , , , Subject: [PATCH v2 1/3] PCI: microchip: Fix outbound address translation tables Date: Mon, 10 Jun 2024 13:18:20 +0100 Message-ID: <20240610121822.2636971-2-daire.mcnamara@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240610121822.2636971-1-daire.mcnamara@microchip.com> References: <20240610121822.2636971-1-daire.mcnamara@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240610_051935_490938_88FDE4A9 X-CRM114-Status: GOOD ( 12.76 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Daire McNamara On Microchip PolarFire SoC (MPFS) the PCIe Root Port can be behind one of three general-purpose Fabric Interface Controller (FIC) buses that encapsulate an AXI-M interface. That FIC is responsible for managing the translations of the upper 32-bits of the AXI-M address. On MPFS, the Root Port driver needs to take account of that outbound address translation done by the parent FIC bus before setting up its own outbound address translation tables. In all cases on MPFS, the remaining outbound address translation tables are 32-bit only. Limit the outbound address translation tables to 32-bit only. Fixes: 6f15a9c9f941 ("PCI: microchip: Add Microchip Polarfire PCIe controller driver") Signed-off-by: Daire McNamara --- drivers/pci/controller/pcie-microchip-host.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/pci/controller/pcie-microchip-host.c b/drivers/pci/controller/pcie-microchip-host.c index 137fb8570ba2..853adce24492 100644 --- a/drivers/pci/controller/pcie-microchip-host.c +++ b/drivers/pci/controller/pcie-microchip-host.c @@ -933,7 +933,7 @@ static int mc_pcie_init_irq_domains(struct mc_pcie *port) static void mc_pcie_setup_window(void __iomem *bridge_base_addr, u32 index, phys_addr_t axi_addr, phys_addr_t pci_addr, - size_t size) + u64 size) { u32 atr_sz = ilog2(size) - 1; u32 val; @@ -983,7 +983,8 @@ static int mc_pcie_setup_windows(struct platform_device *pdev, if (resource_type(entry->res) == IORESOURCE_MEM) { pci_addr = entry->res->start - entry->offset; mc_pcie_setup_window(bridge_base_addr, index, - entry->res->start, pci_addr, + entry->res->start & 0xffffffff, + pci_addr, resource_size(entry->res)); index++; } @@ -1117,9 +1118,8 @@ static int mc_platform_init(struct pci_config_window *cfg) int ret; /* Configure address translation table 0 for PCIe config space */ - mc_pcie_setup_window(bridge_base_addr, 0, cfg->res.start, - cfg->res.start, - resource_size(&cfg->res)); + mc_pcie_setup_window(bridge_base_addr, 0, cfg->res.start & 0xffffffff, + 0, resource_size(&cfg->res)); /* Need some fixups in config space */ mc_pcie_enable_msi(port, cfg->win);