From patchwork Wed Jun 12 11:22:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daire McNamara X-Patchwork-Id: 13694848 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C797FC2BA12 for ; Wed, 12 Jun 2024 11:23:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=u4qcYcRNgSkpjXx9Z0m7FGJW/OY+Lv1FfsvZpcrarnQ=; b=LJfnl/TJ30n+ol vLN8AjAiThESFsk2kwdcnqVaQ3w5sHScvW7DsnrWp9EeAUbGyZejz2r/wZsvWBrQCIMQOaPaXlhTT ShbQouNSgVpCe+9Rm75InGcElXtAdcJGJbcFVWvT1ZUKc8GDqTnBpURF4synGqEmewU+eL0G6ZUVv IvDaE1nVaFmFEY11fSCokUGWej2rqfdLpdDgy9a/iJWepDfTjbjeWC62rl00rmWlXGyAVbDEtg/ED nWPiIeefmsgw0h5NRU1P2KZteMjazBANkIVPWcxvVQ2r0UD0htc1chcY6FaHTFStOHQ5lS8PmN/Xg uIWsVNCruE4PCPMk4Tig==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sHM4d-0000000CQV6-3td5; Wed, 12 Jun 2024 11:23:27 +0000 Received: from esa.microchip.iphmx.com ([68.232.153.233]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sHM4a-0000000CQSc-1myR for linux-riscv@lists.infradead.org; Wed, 12 Jun 2024 11:23:26 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1718191404; x=1749727404; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=oFdeEmSZCx2CmTI24Mlau+qRlUsKvxGoVQk9WMKPt7Y=; b=ifFdRGoDY89i2gjLGeb/uUzdBX/NmwNuEe9JTu0Zv9kp8lxVNi7+iwob 5gORyXYAMH7ZpxujWSQ8r7hLcpYl3BHBYzBEdTn3OIRIA0C8ioU1figo+ LOw9wqWqedzsX8z4VwPC84ioRDCTiWCY8dgA2XPVEinpMf8ENxyxpa2f1 k1gBTpSmrmzgwclL2d8XEJPntb1MD1KXifrC93+hn8qPfOWMNM3Sv0UbX oItlTRbGxtwJb78iKioExDDluQ0HHG8GF+D4N9zcupQmZaAHs2xbv4toh fMTVKaNg9i4rTk4VDlAN3Ry+YdFpshmaOKe/cRLdFjI6Xj0wM73jhjZWV w==; X-CSE-ConnectionGUID: hzPuRHFvRM+Wy8rrRTyffQ== X-CSE-MsgGUID: 0FhutBR6Rw27WmRvE+rb1A== X-IronPort-AV: E=Sophos;i="6.08,233,1712646000"; d="scan'208";a="29761705" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 12 Jun 2024 04:23:22 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 12 Jun 2024 04:22:46 -0700 Received: from daire-X570.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Wed, 12 Jun 2024 04:22:43 -0700 From: To: , CC: , , , , , , , , , Subject: [PATCH v3 1/3] PCI: microchip: Fix outbound address translation tables Date: Wed, 12 Jun 2024 12:22:11 +0100 Message-ID: <20240612112213.2734748-2-daire.mcnamara@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240612112213.2734748-1-daire.mcnamara@microchip.com> References: <20240612112213.2734748-1-daire.mcnamara@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240612_042324_676154_222F3577 X-CRM114-Status: GOOD ( 13.05 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Daire McNamara On Microchip PolarFire SoC (MPFS) the PCIe Root Port can be behind one of three general-purpose Fabric Interface Controller (FIC) buses that encapsulate an AXI-M interface. That FIC is responsible for managing the translations of the upper 32-bits of the AXI-M address. On MPFS, the Root Port driver needs to take account of that outbound address translation done by the parent FIC bus before setting up its own outbound address translation tables. In all cases on MPFS, the remaining outbound address translation tables are 32-bit only. Limit the outbound address translation tables to 32-bit only. Fixes: 6f15a9c9f941 ("PCI: microchip: Add Microchip Polarfire PCIe controller driver") Signed-off-by: Daire McNamara --- drivers/pci/controller/pcie-microchip-host.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/pci/controller/pcie-microchip-host.c b/drivers/pci/controller/pcie-microchip-host.c index 137fb8570ba2..853adce24492 100644 --- a/drivers/pci/controller/pcie-microchip-host.c +++ b/drivers/pci/controller/pcie-microchip-host.c @@ -933,7 +933,7 @@ static int mc_pcie_init_irq_domains(struct mc_pcie *port) static void mc_pcie_setup_window(void __iomem *bridge_base_addr, u32 index, phys_addr_t axi_addr, phys_addr_t pci_addr, - size_t size) + u64 size) { u32 atr_sz = ilog2(size) - 1; u32 val; @@ -983,7 +983,8 @@ static int mc_pcie_setup_windows(struct platform_device *pdev, if (resource_type(entry->res) == IORESOURCE_MEM) { pci_addr = entry->res->start - entry->offset; mc_pcie_setup_window(bridge_base_addr, index, - entry->res->start, pci_addr, + entry->res->start & 0xffffffff, + pci_addr, resource_size(entry->res)); index++; } @@ -1117,9 +1118,8 @@ static int mc_platform_init(struct pci_config_window *cfg) int ret; /* Configure address translation table 0 for PCIe config space */ - mc_pcie_setup_window(bridge_base_addr, 0, cfg->res.start, - cfg->res.start, - resource_size(&cfg->res)); + mc_pcie_setup_window(bridge_base_addr, 0, cfg->res.start & 0xffffffff, + 0, resource_size(&cfg->res)); /* Need some fixups in config space */ mc_pcie_enable_msi(port, cfg->win);