RISC-V: Provide the frequency of mtime via hwprobe

Commit Message

Yunhui Cui June 18, 2024, 11:46 a.m. UTC

From: Palmer Dabbelt <[e-mail]>

A handful of user-visible behavior is based on the frequency of the
machine-mode time.

Signed-off-by: Palmer Dabbelt <[e-mail]>
Signed-off-by: Yunhui Cui <[e-mail]>
---
 Documentation/arch/riscv/hwprobe.rst  | 2 ++
 arch/riscv/include/asm/hwprobe.h      | 2 +-
 arch/riscv/include/uapi/asm/hwprobe.h | 1 +
 arch/riscv/kernel/sys_hwprobe.c       | 5 +++++
 4 files changed, 9 insertions(+), 1 deletion(-)

Comments

Jessica Clarke June 18, 2024, 5:11 p.m. UTC | #1

On 18 Jun 2024, at 12:46, Yunhui Cui <[e-mail]> wrote:
> 
> From: Palmer Dabbelt <[e-mail]>
> 
> A handful of user-visible behavior is based on the frequency of the
> machine-mode time.
> 
> Signed-off-by: Palmer Dabbelt <[e-mail]>
> Signed-off-by: Yunhui Cui <[e-mail]>

I would suggest referring to the user-mode CSR instead, i.e. “time”
rather than “mtime” throughout in names and descriptions, since that’s
the thing that user-mode software is actually reading from.

Jess

Icenowy Zheng June 18, 2024, 11:51 p.m. UTC | #2

在 2024-06-18星期二的 18:11 +0100，Jessica Clarke写道：
> On 18 Jun 2024, at 12:46, Yunhui Cui <[e-mail]> wrote:
> > 
> > From: Palmer Dabbelt <[e-mail]>
> > 
> > A handful of user-visible behavior is based on the frequency of the
> > machine-mode time.
> > 
> > Signed-off-by: Palmer Dabbelt <[e-mail]>
> > Signed-off-by: Yunhui Cui <[e-mail]>
> 
> I would suggest referring to the user-mode CSR instead, i.e. “time”
> rather than “mtime” throughout in names and descriptions, since
> that’s
> the thing that user-mode software is actually reading from.

Agree. MTIME isn't even a thing defined in RISC-V ISA -- it's part of
the ACLINT timer spec, but before ACLINT gets widely accepted, it's
just some SiFive thing that got copied by many other vendors (and
vendors such as T-Head even provides CLINT w/o MTIME register (well
because these T-Head cores have reference source code available, this
is because of their CPU design uses an external counter fed as TIME
register)).

> 
> Jess
> 
> 
> _______________________________________________
> linux-riscv mailing list
> [e-mail]
> http://lists.infradead.org/mailman/listinfo/linux-riscv

Yunhui Cui June 21, 2024, 3:01 a.m. UTC | #3

Hi Icenowy,

On Wed, Jun 19, 2024 at 7:51 AM Icenowy Zheng <[e-mail]> wrote:
>
> 在 2024-06-18星期二的 18:11 +0100，Jessica Clarke写道：
> > On 18 Jun 2024, at 12:46, Yunhui Cui <[e-mail]> wrote:
> > >
> > > From: Palmer Dabbelt <[e-mail]>
> > >
> > > A handful of user-visible behavior is based on the frequency of the
> > > machine-mode time.
> > >
> > > Signed-off-by: Palmer Dabbelt <[e-mail]>
> > > Signed-off-by: Yunhui Cui <[e-mail]>
> >
> > I would suggest referring to the user-mode CSR instead, i.e. “time”
> > rather than “mtime” throughout in names and descriptions, since
> > that’s
> > the thing that user-mode software is actually reading from.
>
> Agree. MTIME isn't even a thing defined in RISC-V ISA -- it's part of
> the ACLINT timer spec, but before ACLINT gets widely accepted, it's
> just some SiFive thing that got copied by many other vendors (and
> vendors such as T-Head even provides CLINT w/o MTIME register (well
> because these T-Head cores have reference source code available, this
> is because of their CPU design uses an external counter fed as TIME
> register)).

Okay, Thanks for your suggestions,  I think this modification is more
appropriate:

RISC-V: Provide the frequency of time counter via hwprobe

A handful of user-visible behavior is based on the frequency of the
time counter.

What do you think ?

>
> >
> > Jess
> >
> >
> > _______________________________________________
> > linux-riscv mailing list
> > [e-mail]
> > http://lists.infradead.org/mailman/listinfo/linux-riscv
>

Thanks,
Yunhui

Icenowy Zheng June 21, 2024, 5:18 a.m. UTC | #4

在 2024-06-21星期五的 11:01 +0800，yunhui cui写道：
> Hi Icenowy,
> 
> On Wed, Jun 19, 2024 at 7:51 AM Icenowy Zheng <[e-mail]> wrote:
> > 
> > 在 2024-06-18星期二的 18:11 +0100，Jessica Clarke写道：
> > > On 18 Jun 2024, at 12:46, Yunhui Cui <[e-mail]>
> > > wrote:
> > > > 
> > > > From: Palmer Dabbelt <[e-mail]>
> > > > 
> > > > A handful of user-visible behavior is based on the frequency of
> > > > the
> > > > machine-mode time.
> > > > 
> > > > Signed-off-by: Palmer Dabbelt <[e-mail]>
> > > > Signed-off-by: Yunhui Cui <[e-mail]>
> > > 
> > > I would suggest referring to the user-mode CSR instead, i.e.
> > > “time”
> > > rather than “mtime” throughout in names and descriptions, since
> > > that’s
> > > the thing that user-mode software is actually reading from.
> > 
> > Agree. MTIME isn't even a thing defined in RISC-V ISA -- it's part
> > of
> > the ACLINT timer spec, but before ACLINT gets widely accepted, it's
> > just some SiFive thing that got copied by many other vendors (and
> > vendors such as T-Head even provides CLINT w/o MTIME register (well
> > because these T-Head cores have reference source code available,
> > this
> > is because of their CPU design uses an external counter fed as TIME
> > register)).
> 
> Okay, Thanks for your suggestions,  I think this modification is more
> appropriate:
> 
> RISC-V: Provide the frequency of time counter via hwprobe

Sure, or you could just say time CSR, which is a defined CSR in the
user ISA document, and allow to be read from userspace.

> 
> A handful of user-visible behavior is based on the frequency of the
> time counter.
> 
> What do you think ?
> 
> > 
> > > 
> > > Jess
> > > 
> > > 
> > > _______________________________________________
> > > linux-riscv mailing list
> > > [e-mail]
> > > http://lists.infradead.org/mailman/listinfo/linux-riscv
> > 
> 
> Thanks,
> Yunhui

Yunhui Cui June 21, 2024, 10:34 a.m. UTC | #5

Hi Icenowy,

On Fri, Jun 21, 2024 at 1:18 PM Icenowy Zheng <[e-mail]> wrote:
>
> 在 2024-06-21星期五的 11:01 +0800，yunhui cui写道：
> > Hi Icenowy,
> >
> > On Wed, Jun 19, 2024 at 7:51 AM Icenowy Zheng <[e-mail]> wrote:
> > >
> > > 在 2024-06-18星期二的 18:11 +0100，Jessica Clarke写道：
> > > > On 18 Jun 2024, at 12:46, Yunhui Cui <[e-mail]>
> > > > wrote:
> > > > >
> > > > > From: Palmer Dabbelt <[e-mail]>
> > > > >
> > > > > A handful of user-visible behavior is based on the frequency of
> > > > > the
> > > > > machine-mode time.
> > > > >
> > > > > Signed-off-by: Palmer Dabbelt <[e-mail]>
> > > > > Signed-off-by: Yunhui Cui <[e-mail]>
> > > >
> > > > I would suggest referring to the user-mode CSR instead, i.e.
> > > > “time”
> > > > rather than “mtime” throughout in names and descriptions, since
> > > > that’s
> > > > the thing that user-mode software is actually reading from.
> > >
> > > Agree. MTIME isn't even a thing defined in RISC-V ISA -- it's part
> > > of
> > > the ACLINT timer spec, but before ACLINT gets widely accepted, it's
> > > just some SiFive thing that got copied by many other vendors (and
> > > vendors such as T-Head even provides CLINT w/o MTIME register (well
> > > because these T-Head cores have reference source code available,
> > > this
> > > is because of their CPU design uses an external counter fed as TIME
> > > register)).
> >
> > Okay, Thanks for your suggestions,  I think this modification is more
> > appropriate:
> >
> > RISC-V: Provide the frequency of time counter via hwprobe
>
> Sure, or you could just say time CSR, which is a defined CSR in the
> user ISA document, and allow to be read from userspace.
>
Okay, I will update it on v2.

> >
> > A handful of user-visible behavior is based on the frequency of the
> > time counter.
> >
> > What do you think ?
> >
> > >
> > > >
> > > > Jess
> > > >
> > > >
> > > > _______________________________________________
> > > > linux-riscv mailing list
> > > > [e-mail]
> > > > http://lists.infradead.org/mailman/listinfo/linux-riscv
> > >
> >
> > Thanks,
> > Yunhui
>

Thanks,
Yunhui

Patch

diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
index fc015b452ebf..0cc3ef5b5541 100644
--- a/Documentation/arch/riscv/hwprobe.rst
+++ b/Documentation/arch/riscv/hwprobe.rst
@@ -229,3 +229,5 @@  The following keys are defined:
 
 * :c:macro:`RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE`: An unsigned int which
   represents the size of the Zicboz block in bytes.
+
+* :c:macro:`RISCV_HWPROBE_KEY_MTIME_FREQ`: Frequency (in Hz) of `mtime`.
diff --git a/arch/riscv/include/asm/hwprobe.h b/arch/riscv/include/asm/hwprobe.h
index 630507dff5ea..150a9877b0af 100644
--- a/arch/riscv/include/asm/hwprobe.h
+++ b/arch/riscv/include/asm/hwprobe.h
@@ -8,7 +8,7 @@ 
 
 #include <uapi/asm/hwprobe.h>
 
-#define RISCV_HWPROBE_MAX_KEY 6
+#define RISCV_HWPROBE_MAX_KEY 7
 
 static inline bool riscv_hwprobe_key_is_valid(__s64 key)
 {
diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
index 7b95fadbea2a..f7d9646ff4ba 100644
--- a/arch/riscv/include/uapi/asm/hwprobe.h
+++ b/arch/riscv/include/uapi/asm/hwprobe.h
@@ -73,6 +73,7 @@  struct riscv_hwprobe {
 #define		RISCV_HWPROBE_MISALIGNED_UNSUPPORTED	(4 << 0)
 #define		RISCV_HWPROBE_MISALIGNED_MASK		(7 << 0)
 #define RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE	6
+#define RISCV_HWPROBE_KEY_MTIME_FREQ	7
 /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */
 
 /* Flags */
diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
index 83fcc939df67..3fa519035416 100644
--- a/arch/riscv/kernel/sys_hwprobe.c
+++ b/arch/riscv/kernel/sys_hwprobe.c
@@ -8,6 +8,7 @@ 
 #include <asm/cacheflush.h>
 #include <asm/cpufeature.h>
 #include <asm/hwprobe.h>
+#include <asm/delay.h>
 #include <asm/sbi.h>
 #include <asm/switch_to.h>
 #include <asm/uaccess.h>
@@ -226,6 +227,10 @@  static void hwprobe_one_pair(struct riscv_hwprobe *pair,
 			pair->value = riscv_cboz_block_size;
 		break;
 
+	case RISCV_HWPROBE_KEY_MTIME_FREQ:
+		pair->value = riscv_timebase;
+		break;
+
 	/*
 	 * For forward compatibility, unknown keys don't fail the whole
 	 * call, but get their element key set to -1 and value set to 0