From patchwork Fri Jun 28 11:59:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Daire McNamara X-Patchwork-Id: 13716013 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7A3B7C30658 for ; Fri, 28 Jun 2024 12:00:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=qK6xIM0pV+FTE9Uo6kaAlY9Ea6JxGt7I6kcv7J0RJGg=; b=x979OclTan0ePw XnTCi8++0PGO9FSKZlnOxpBKqKLGcARNObp2jIVLxNEazArRO/cx+7C6dja8NayKSSMmS2PVhU2Vk 1kGdFylhiAEz0qBRknO1BemwbwAmawq4NrhSikexrIMt6LQr5pWocsigPejU8mR0Ep6AasCHUePCJ QATgm4Dr3eozKJeo+BQa6IvX2d9FAKWsvN79zGYzKxsffojqCeBd8Q1+JsPKNIOA86Slh5ZPWEYQs eNq7SO89jBfAcNQBIfEHWWtMqdbWTjZvKd1+GEhIq4IGTd4tmRwbPo8unwjMkOtzPnK7GQFao/xGq lBJ9x1k0dXyE17NGDz6A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sNAGt-0000000DcB6-3AWm; Fri, 28 Jun 2024 12:00:07 +0000 Received: from esa.microchip.iphmx.com ([68.232.153.233]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sNAGp-0000000Dc8e-1zTW for linux-riscv@lists.infradead.org; Fri, 28 Jun 2024 12:00:04 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1719576003; x=1751112003; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=pnR4pmsg5MGAcoqhuGjuhjHJEgVUH86UycujeWipnZw=; b=izikoAxUa7ulJc9/fji5uks23VLbzs+g49up9E/X615W73oG6jXFfjyk 2AZtFNWEhORe8PsGDTOAE2tQuqsyOmizRpPKoXa8tlT7NMSKscKmq8uMj al1kto463RFX/mFaPc5I27EntahG97fZ3WHGS4ESoG5rP9qfwGPKFVr3t BFRBVgM7RxzLmJvbuz9zFvwvJ1O6dhJDUihw42YjOX5NClt8WpBm4UJef ulxaFtPFtziSP7RAEJ4n84gdEj8RkUPglJ8vMHtJG6iJucOko10eldZBF O+8vUtr8sB+rXTkYio21jFQNqKKvSUmgZMpz7FMTolM82z84n5W9cwGGZ Q==; X-CSE-ConnectionGUID: fhzcQ281QiKf1QfzQI0hzg== X-CSE-MsgGUID: 7a9N9JiwQoaqIAb8otbLqA== X-IronPort-AV: E=Sophos;i="6.09,169,1716274800"; d="scan'208";a="259502560" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 28 Jun 2024 05:00:00 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Fri, 28 Jun 2024 04:59:27 -0700 Received: from daire-X570.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Fri, 28 Jun 2024 04:59:25 -0700 From: To: , CC: , , , , , , , , , , Subject: [PATCH v6 1/3] PCI: microchip: Fix outbound address translation tables Date: Fri, 28 Jun 2024 12:59:21 +0100 Message-ID: <20240628115923.4133286-2-daire.mcnamara@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240628115923.4133286-1-daire.mcnamara@microchip.com> References: <20240628115923.4133286-1-daire.mcnamara@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240628_050003_619825_BD45CE7A X-CRM114-Status: GOOD ( 13.48 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Daire McNamara On Microchip PolarFire SoC (MPFS) the PCIe Root Port can be behind one of three general-purpose Fabric Interface Controller (FIC) buses that encapsulate an AXI-M interface. That FIC is responsible for managing the translations of the upper 32-bits of the AXI-M address. On MPFS, the Root Port driver needs to take account of that outbound address translation done by the parent FIC bus before setting up its own outbound address translation tables. In all cases on MPFS, the remaining outbound address translation tables are 32-bit only. Limit the outbound address translation tables to 32-bit only. This necessitates changing a size_t in mc_pcie_setup_window to a resource_size_t to avoid a compile error on 32-bit platforms. Fixes: 6f15a9c9f941 ("PCI: microchip: Add Microchip Polarfire PCIe controller driver") Signed-off-by: Daire McNamara Acked-by: Conor Dooley Reviewed-by: Ilpo Järvinen --- drivers/pci/controller/pcie-microchip-host.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/pci/controller/pcie-microchip-host.c b/drivers/pci/controller/pcie-microchip-host.c index 137fb8570ba2..47c397ae515a 100644 --- a/drivers/pci/controller/pcie-microchip-host.c +++ b/drivers/pci/controller/pcie-microchip-host.c @@ -23,6 +23,8 @@ /* Number of MSI IRQs */ #define MC_MAX_NUM_MSI_IRQS 32 +#define MC_OUTBOUND_TRANS_TBL_MASK GENMASK(31, 0) + /* PCIe Bridge Phy and Controller Phy offsets */ #define MC_PCIE1_BRIDGE_ADDR 0x00008000u #define MC_PCIE1_CTRL_ADDR 0x0000a000u @@ -933,7 +935,7 @@ static int mc_pcie_init_irq_domains(struct mc_pcie *port) static void mc_pcie_setup_window(void __iomem *bridge_base_addr, u32 index, phys_addr_t axi_addr, phys_addr_t pci_addr, - size_t size) + resource_size_t size) { u32 atr_sz = ilog2(size) - 1; u32 val; @@ -983,7 +985,8 @@ static int mc_pcie_setup_windows(struct platform_device *pdev, if (resource_type(entry->res) == IORESOURCE_MEM) { pci_addr = entry->res->start - entry->offset; mc_pcie_setup_window(bridge_base_addr, index, - entry->res->start, pci_addr, + entry->res->start & MC_OUTBOUND_TRANS_TBL_MASK, + pci_addr, resource_size(entry->res)); index++; } @@ -1117,9 +1120,8 @@ static int mc_platform_init(struct pci_config_window *cfg) int ret; /* Configure address translation table 0 for PCIe config space */ - mc_pcie_setup_window(bridge_base_addr, 0, cfg->res.start, - cfg->res.start, - resource_size(&cfg->res)); + mc_pcie_setup_window(bridge_base_addr, 0, cfg->res.start & MC_OUTBOUND_TRANS_TBL_MASK, + 0, resource_size(&cfg->res)); /* Need some fixups in config space */ mc_pcie_enable_msi(port, cfg->win);