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Thu, 01 Aug 2024 11:38:24 -0700 (PDT) Received: from [127.0.1.1] ([2601:1c2:1802:170:dfa1:41a7:9478:9d47]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2cffaf69d54sm279728a91.12.2024.08.01.11.38.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Aug 2024 11:38:23 -0700 (PDT) From: Drew Fustini Date: Thu, 01 Aug 2024 11:38:07 -0700 Subject: [PATCH 3/6] riscv: dts: thead: change TH1520 mmc nodes to use clock controller MIME-Version: 1.0 Message-Id: <20240801-th1520-clk-dts-v1-3-71077a0614b8@pdp7.com> References: <20240801-th1520-clk-dts-v1-0-71077a0614b8@pdp7.com> In-Reply-To: <20240801-th1520-clk-dts-v1-0-71077a0614b8@pdp7.com> To: Emil Renner Berthing , Thomas Bonnefille , Kanak Shilledar , Jisheng Zhang , Guo Ren , Fu Wei , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Drew Fustini , Drew Fustini X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=2960; i=drew@pdp7.com; h=from:subject:message-id; bh=YuaP04LUjcDqw71tzI0qnQ5/4oo5IjakGbRJi9B2Yv4=; b=owGbwMvMwCF2+43O4ZsaG3kYT6slMaStviZ1I9lFu9CO7WBeRnGBVKrm0Y9916xmHWGReh7Id 6nPZP73jlIWBjEOBlkxRZZNH/IuLPEK/bpg/ottMHNYmUCGMHBxCsBN/sPwz0xuy+PMhQ1l6W71 jO9XvvXYtOXHY+0HO3QlfZcHnOiPvsLIcLiy+63V0+SL+zbsVv56y8lpzozTpXksd34mfg348iI 6gBkA X-Developer-Key: i=drew@pdp7.com; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240801_113825_106578_CB397221 X-CRM114-Status: GOOD ( 10.38 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Drew Fustini Change the clock property in the TH1520 mmc controller nodes to a clock provided by AP_SYS clock controller. Remove sdhci fixed clock reference from BeagleV Ahead and LPI4a dts. Link: https://git.beagleboard.org/beaglev-ahead/beaglev-ahead/-/tree/main/docs Signed-off-by: Drew Fustini --- arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts | 4 ---- arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi | 4 ---- arch/riscv/boot/dts/thead/th1520.dtsi | 13 +++---------- 3 files changed, 3 insertions(+), 18 deletions(-) diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts index 90585883b059..5169a718f79c 100644 --- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts +++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts @@ -49,10 +49,6 @@ &apb_clk { clock-frequency = <62500000>; }; -&sdhci_clk { - clock-frequency = <198000000>; -}; - &spi_clk { clock-frequency = <396000000>; }; diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi index 1c5c7075ae17..be982a3ac18c 100644 --- a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi +++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi @@ -29,10 +29,6 @@ &apb_clk { clock-frequency = <62500000>; }; -&sdhci_clk { - clock-frequency = <198000000>; -}; - &spi_clk { clock-frequency = <396000000>; }; diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi index a543be8d6e37..f3b2f8236096 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -228,13 +228,6 @@ spi_clk: spi-clock { #clock-cells = <0>; }; - sdhci_clk: sdhci-clock { - compatible = "fixed-clock"; - clock-frequency = <198000000>; - clock-output-names = "sdhci_clk"; - #clock-cells = <0>; - }; - soc { compatible = "simple-bus"; interrupt-parent = <&plic>; @@ -290,7 +283,7 @@ emmc: mmc@ffe7080000 { compatible = "thead,th1520-dwcmshc"; reg = <0xff 0xe7080000 0x0 0x10000>; interrupts = <62 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&sdhci_clk>; + clocks = <&clk CLK_EMMC_SDIO>; clock-names = "core"; status = "disabled"; }; @@ -299,7 +292,7 @@ sdio0: mmc@ffe7090000 { compatible = "thead,th1520-dwcmshc"; reg = <0xff 0xe7090000 0x0 0x10000>; interrupts = <64 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&sdhci_clk>; + clocks = <&clk CLK_EMMC_SDIO>; clock-names = "core"; status = "disabled"; }; @@ -308,7 +301,7 @@ sdio1: mmc@ffe70a0000 { compatible = "thead,th1520-dwcmshc"; reg = <0xff 0xe70a0000 0x0 0x10000>; interrupts = <71 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&sdhci_clk>; + clocks = <&clk CLK_EMMC_SDIO>; clock-names = "core"; status = "disabled"; };