From patchwork Wed Aug 21 13:02:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daire McNamara X-Patchwork-Id: 13771674 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5A8DEC52D6F for ; Wed, 21 Aug 2024 14:15:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=OKSez3CXSQO1kjrpUrXdMYCVub3zooUvP7OjXhWZza4=; b=LKMXtapT/dc4JS JCdyf/PJlT/vRbcAyR5QiBd6TuVF+PTuD+j65pc5ZEkD51cLRG+kg7Wevs+nxcoKzF164q8wVEXpl TqDOo5GBooIEPpgrL9sidtcZUDymfTORKPaoc00itcbB1N/X7pRv2H4Jv0aoIYHYZM8eTcQELjWAU +w1zDla5gDd/h0pKhrE7uDbZFLUhXwFvMr0DunrxFvHWRE4yr4j356LbbD7AT8eBFo0kysn5eRJ8G wqKZlp3WjzzByNhBiqLZKz2qzz0RR47ufUbIzSVamkIQER+Ufu7jf551x1JZZ0fkJKFHYeuvT8zSc +E8US7ATzcxxeQZV7D7A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sgm7l-00000009Fhe-3RwQ; Wed, 21 Aug 2024 14:15:45 +0000 Received: from esa.microchip.iphmx.com ([68.232.153.233]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sgkzI-000000091H8-0nHe for linux-riscv@lists.infradead.org; Wed, 21 Aug 2024 13:02:57 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1724245376; x=1755781376; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ITGSnwUlbEDRh69Ym2WWBpy0Jt4APraANaGuUfDwMiA=; b=pOl0hjYqbXhj5IXkEaH7IF8XidOCzVRrv6RKNDi0k5Ii2tn2V28amTlq 3ereYm7CoTQkNKfIKq9dx7XVZAptpIyMYkS2BgTCcIDCGUiHBENT2oI2y l263NsRkc5IQoDF46vzGS69dx0T/DmfXW8MZLslVDRxiMlbtPKkfgwKcm 2TicUCsmG+AtyEq7VX1iVrEprjiXskxoYOMBk32q1eMAvIkmWPwrdxyrj ocho1DcxJAaxnLhvfhcV/2F9XlFHw8RSkxrRb0i7abB8JBwScmAn/UCWj p40rcu+1n139kAArwNYmLTdmnCiCsZ3logc99I313pStlJA2kHhMi3+Fn A==; X-CSE-ConnectionGUID: hYt9Btb/Rtq04w/yiOUfIw== X-CSE-MsgGUID: cwDKoYQDQBCF1aifJpkXLQ== X-IronPort-AV: E=Sophos;i="6.10,164,1719903600"; d="scan'208";a="30743853" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 21 Aug 2024 06:02:52 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 21 Aug 2024 06:02:32 -0700 Received: from daire-X570.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Wed, 21 Aug 2024 06:02:30 -0700 From: To: , CC: , , , , , , , , , , Subject: [PATCH v8 1/3] PCI: microchip: Fix outbound address translation tables Date: Wed, 21 Aug 2024 14:02:15 +0100 Message-ID: <20240821130217.957424-2-daire.mcnamara@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240821130217.957424-1-daire.mcnamara@microchip.com> References: <20240821130217.957424-1-daire.mcnamara@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240821_060256_264539_0B5FC531 X-CRM114-Status: GOOD ( 16.84 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Daire McNamara On Microchip PolarFire SoC (MPFS) the PCIe Root Port can be behind one of three general-purpose Fabric Interface Controller (FIC) buses that encapsulate an AXI-M interface. That FIC is responsible for managing the translations of the upper 32-bits of the AXI-M address. On MPFS, the Root Port driver needs to take account of that outbound address translation done by the parent FIC bus before setting up its own outbound address translation tables. In all cases on MPFS, the remaining outbound address translation tables are 32-bit only. Limit the outbound address translation tables to 32-bit only. This necessitates changing a size_t in mc_pcie_setup_window to a u64 to avoid a compile error on 32-bit platforms. Fixes: 6f15a9c9f941 ("PCI: microchip: Add Microchip Polarfire PCIe controller driver") Signed-off-by: Daire McNamara Acked-by: Conor Dooley Reviewed-by: Ilpo Jarvinen --- .../pci/controller/plda/pcie-microchip-host.c | 30 ++++++++++++++++--- 1 file changed, 26 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/plda/pcie-microchip-host.c b/drivers/pci/controller/plda/pcie-microchip-host.c index 48f60a04b740..da766de347bd 100644 --- a/drivers/pci/controller/plda/pcie-microchip-host.c +++ b/drivers/pci/controller/plda/pcie-microchip-host.c @@ -21,6 +21,8 @@ #include "../../pci.h" #include "pcie-plda.h" +#define MC_OUTBOUND_TRANS_TBL_MASK GENMASK(31, 0) + /* PCIe Bridge Phy and Controller Phy offsets */ #define MC_PCIE1_BRIDGE_ADDR 0x00008000u #define MC_PCIE1_CTRL_ADDR 0x0000a000u @@ -612,6 +614,27 @@ static void mc_disable_interrupts(struct mc_pcie *port) writel_relaxed(GENMASK(31, 0), bridge_base_addr + ISTATUS_HOST); } +int mc_pcie_setup_iomems(struct pci_host_bridge *bridge, + struct plda_pcie_rp *port) +{ + void __iomem *bridge_base_addr = port->bridge_addr; + struct resource_entry *entry; + u64 pci_addr; + u32 index = 1; + + resource_list_for_each_entry(entry, &bridge->windows) { + if (resource_type(entry->res) == IORESOURCE_MEM) { + pci_addr = entry->res->start - entry->offset; + plda_pcie_setup_window(bridge_base_addr, index, + entry->res->start & MC_OUTBOUND_TRANS_TBL_MASK, + pci_addr, resource_size(entry->res)); + index++; + } + } + + return 0; +} + static int mc_platform_init(struct pci_config_window *cfg) { struct device *dev = cfg->parent; @@ -622,15 +645,14 @@ static int mc_platform_init(struct pci_config_window *cfg) int ret; /* Configure address translation table 0 for PCIe config space */ - plda_pcie_setup_window(bridge_base_addr, 0, cfg->res.start, - cfg->res.start, - resource_size(&cfg->res)); + plda_pcie_setup_window(bridge_base_addr, 0, cfg->res.start & MC_OUTBOUND_TRANS_TBL_MASK, + 0, resource_size(&cfg->res)); /* Need some fixups in config space */ mc_pcie_enable_msi(port, cfg->win); /* Configure non-config space outbound ranges */ - ret = plda_pcie_setup_iomems(bridge, &port->plda); + ret = mc_pcie_setup_iomems(bridge, &port->plda); if (ret) return ret;