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AJvYcCWFHTqpTVNFC2efF+vNvPqZJlGjUS+0WsWvyz7ExWJel+I6+sCOQVQLbtYUOr2Lz84++jGXPTCJBh/K8A==@lists.infradead.org X-Gm-Message-State: AOJu0YwAiGfGmBUuQdiaRPPzsObcDFWL5fJF+dCBAdFu5OG+WykXNwtX 8UEV53PRG0PmS+cC3ZXUz9xsRlJWTLDGH5tUY0pM5C13z73hc8tX X-Google-Smtp-Source: AGHT+IGPTeZzgwWJYrCDC9+6ULWhqzz+N66BwcmM+1R3Eh86zl3oXyQ3q54ErbKwTAYcAwPG5dUmYQ== X-Received: by 2002:a05:600c:46c5:b0:42c:b843:792b with SMTP id 5b1f17b1804b1-42cdb531b96mr40618205e9.2.1726204440453; Thu, 12 Sep 2024 22:14:00 -0700 (PDT) Received: from localhost.localdomain ([37.72.3.43]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42d9b15c2f4sm11063685e9.24.2024.09.12.22.13.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Sep 2024 22:13:59 -0700 (PDT) From: =?utf-8?q?Miquel_Sabat=C3=A9_Sol=C3=A0?= To: paul.walmsley@sifive.com Cc: palmer@dabbelt.com, aou@eecs.berkeley.edu, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, =?utf-8?q?Mi?= =?utf-8?q?quel_Sabat=C3=A9_Sol=C3=A0?= , Jesse Taube , Conor Dooley Subject: [RESEND PATCH v2] riscv: hwprobe: export Zicntr and Zihpm extensions Date: Fri, 13 Sep 2024 07:13:24 +0200 Message-ID: <20240913051324.8176-1-mikisabate@gmail.com> X-Mailer: git-send-email 2.46.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240912_221403_016682_157BB610 X-CRM114-Status: GOOD ( 10.50 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Export Zicntr and Zihpm ISA extensions through the hwprobe syscall. Signed-off-by: Miquel Sabaté Solà Acked-by: Jesse Taube Reviewed-by: Conor Dooley --- This is a resend because I sent v2 as a reply to the original thread and it most probably was lost by most people. Fortunately Conor picked it up and gave it a review. I am resending this so it can be properly applied. Thank you for your time and sorry for the inconvenience. Changes since v1 [1]: the EXT_KEY instructions have been written in order. [1] https://lore.kernel.org/linux-riscv/20240817075629.262318-1-mikisabate@gmail.com/ Documentation/arch/riscv/hwprobe.rst | 6 ++++++ arch/riscv/include/uapi/asm/hwprobe.h | 2 ++ arch/riscv/kernel/sys_hwprobe.c | 2 ++ 3 files changed, 10 insertions(+) -- 2.46.0 diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst index 3db60a0911df..cfd2929d0562 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -183,6 +183,9 @@ The following keys are defined: defined in the Atomic Compare-and-Swap (CAS) instructions manual starting from commit 5059e0ca641c ("update to ratified"). + * :c:macro:`RISCV_HWPROBE_EXT_ZICNTR`: The Zicntr extension version 2.0 + is supported as defined in the RISC-V ISA manual. + * :c:macro:`RISCV_HWPROBE_EXT_ZICOND`: The Zicond extension is supported as defined in the RISC-V Integer Conditional (Zicond) operations extension manual starting from commit 95cf1f9 ("Add changes requested by Ved @@ -192,6 +195,9 @@ The following keys are defined: supported as defined in the RISC-V ISA manual starting from commit d8ab5c78c207 ("Zihintpause is ratified"). + * :c:macro:`RISCV_HWPROBE_EXT_ZIHPM`: The Zihpm extension version 2.0 + is supported as defined in the RISC-V ISA manual. + * :c:macro:`RISCV_HWPROBE_EXT_ZVE32X`: The Vector sub-extension Zve32x is supported, as defined by version 1.0 of the RISC-V Vector extension manual. diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h index b706c8e47b02..098a815b3fd4 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -72,6 +72,8 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZCF (1ULL << 46) #define RISCV_HWPROBE_EXT_ZCMOP (1ULL << 47) #define RISCV_HWPROBE_EXT_ZAWRS (1ULL << 48) +#define RISCV_HWPROBE_EXT_ZICNTR (1ULL << 49) +#define RISCV_HWPROBE_EXT_ZIHPM (1ULL << 50) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c index 8d1b5c35d2a7..910b41b6a7ab 100644 --- a/arch/riscv/kernel/sys_hwprobe.c +++ b/arch/riscv/kernel/sys_hwprobe.c @@ -107,9 +107,11 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, EXT_KEY(ZCB); EXT_KEY(ZCMOP); EXT_KEY(ZICBOZ); + EXT_KEY(ZICNTR); EXT_KEY(ZICOND); EXT_KEY(ZIHINTNTL); EXT_KEY(ZIHINTPAUSE); + EXT_KEY(ZIHPM); EXT_KEY(ZIMOP); EXT_KEY(ZKND); EXT_KEY(ZKNE);