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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7e6b7c73120sm3592352a12.68.2024.09.25.23.56.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Sep 2024 23:56:06 -0700 (PDT) From: Nick Hu To: greentime.hu@sifive.com, zong.li@sifive.com, Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J. Wysocki" , Pavel Machek , Daniel Lezcano , Thomas Gleixner , Anup Patel , Andrew Jones , Mayuresh Chitale , Conor Dooley , Atish Patra , Nick Hu , Samuel Holland , Samuel Ortiz , Sunil V L , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v2 3/3] clocksource/drivers/timer-riscv: Stop stimecmp when cpu hotplug Date: Thu, 26 Sep 2024 14:54:18 +0800 Message-Id: <20240926065422.226518-4-nick.hu@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240926065422.226518-1-nick.hu@sifive.com> References: <20240926065422.226518-1-nick.hu@sifive.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240925_235608_158921_70049D93 X-CRM114-Status: GOOD ( 10.78 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Stop the stimecmp when the cpu is going to be off otherwise the timer stimecmp register while cpu non retention suspend. Suggested-by: Anup Patel Link: https://lore.kernel.org/lkml/20240829033904.477200-3-nick.hu@sifive.com/T/#u Signed-off-by: Nick Hu Reviewed-by: Anup Patel --- drivers/clocksource/timer-riscv.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c index 48ce50c5f5e6..166dee14e46b 100644 --- a/drivers/clocksource/timer-riscv.c +++ b/drivers/clocksource/timer-riscv.c @@ -127,6 +127,12 @@ static int riscv_timer_starting_cpu(unsigned int cpu) static int riscv_timer_dying_cpu(unsigned int cpu) { disable_percpu_irq(riscv_clock_event_irq); + /* + * Stop the timer when the cpu is going to be offline otherwise + * the timer interrupt may be pending while performing power-down. + */ + riscv_clock_event_stop(); + return 0; }