From patchwork Wed Oct 2 16:10:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 13820033 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A8BE5CF6D3C for ; Wed, 2 Oct 2024 16:12:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=c46nBCy3OCDqwQE74/umja/Ts8Ieew3b2L+Xnkl4p1o=; b=WOJmEc9cd4I1Yc vfIIVdD/x57SNur3dt+aE5cr70y8EDgZEbn/FGfIK70C6ifagPWzevY7LpQf2Xfz9xPz1lEUasMAk 9SqYDjMOWypgc40sTuuF7KNevyfBgGMll8q7Y8tgt+QboCyqk4xfw/rJCdsS72jV53s4Mhs4dqVC3 uSc29F+ApmaJjHOmBJf2IqmXBIOnvgkIns6BgfgOXTWiq1AW/4UpdZUkg/O9jrcGl1tesb+26v8WF TdoJN4jEj3t0BaAxY+BfJCk910KO0uX20zL8eycN7Od8JqNPKt1JbaDPL2WOqiAC7lX4nX7mIWo8f L9gCp2CPkJahN9hXos0g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1sw1xP-00000006slT-1YYV; Wed, 02 Oct 2024 16:12:07 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1sw1xN-00000006sjX-0UG8 for linux-riscv@lists.infradead.org; Wed, 02 Oct 2024 16:12:06 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id 766295C4CF7; Wed, 2 Oct 2024 16:12:00 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id D83E8C4CECD; Wed, 2 Oct 2024 16:12:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1727885524; bh=mCRekBHgNwFBX1KL6AOZHvr9N4tmriuM/RvTA6+DVm4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=L2+ayXHhUHPTjpTt4zczWxCqmEwZRf0lUqAhCKLgTv1C+CV+x5ZC4iHkqVY57zvb1 56su9G7BVXOlnkE5Pja9an0r74+kM/pXmKK4WaHNQCPAz+Fmn6Vs431gBlfmRecWti 0SxdL2k/acijFAKrRPctzPMvRon4hLuik0YEn2UxLWaqQuByCFpYHCiPCTJBmHL1Y+ 4u0YDRLBgDkO9CRMryfxb5mWrt9k/DNLsRoO8D+NOiZItjO2v2CsmpaKP32RH8qBWT sjnZryNz41EOCsOl+n8cTBdDD9Q3B1Vav1iqrsnDIAK9USZJLr50hgyHBI2uEoumWq 1iV8G+kKgIHTA== From: Conor Dooley To: linux-riscv@lists.infradead.org Cc: conor@kernel.org, Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Andy Chiu , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC v1 2/5] RISC-V: add f & d extension validation checks Date: Wed, 2 Oct 2024 17:10:55 +0100 Message-ID: <20241002-stuffed-trance-1323386dd80b@spud> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241002-defeat-pavestone-73d712895f0b@spud> References: <20241002-defeat-pavestone-73d712895f0b@spud> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2979; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=xf019LNZCscq0WBMmHr1I5lt/oOvG/GepcaYsq7GDK8=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDGl/C/rF/wSseBJ8bplFDMueWds53hmbbDvbfkr7ofC/0 6xSug+LOkpZGMQ4GGTFFFkSb/e1SK3/47LDuectzBxWJpAhDFycAjCRyz8ZGSYKK63+uab/k2ft rYlFF9Ms/t11XNMck/63fWFOz7aWUFuG/6WhgqGFXKeWnNW4dTPpbtnONzvev91wZlZYn+2hRe5 nsvgA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241002_091205_270400_A5CE5347 X-CRM114-Status: GOOD ( 14.77 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Conor Dooley Using Clement's new validation callbacks, support checking that dependencies have been satisfied for the floating point extensions. The check for "d" might be slightly confusingly shorter than that of "f", despite "d" depending on "f". This is because the requirement that a hart supporting double precision must also support single precision, should be validated by dt-bindings etc, not the kernel but lack of support for single precision only is a limitation of the kernel. Since vector will now be disabled proactively, there's no need to clear the bit in elf_hwcap in riscv_fill_hwcap() any longer. Signed-off-by: Conor Dooley --- arch/riscv/kernel/cpufeature.c | 36 +++++++++++++++++++++++----------- 1 file changed, 25 insertions(+), 11 deletions(-) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 84a2ad2581cb0..b8a22ee76c2ef 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -101,6 +101,29 @@ static int riscv_ext_zicboz_validate(const struct riscv_isa_ext_data *data, return 0; } +static int riscv_ext_f_validate(const struct riscv_isa_ext_data *data, + const unsigned long *isa_bitmap) +{ + if (!__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_d)) { + pr_warn_once("This kernel does not support systems with F but not D\n"); + return -EINVAL; + } + + if (IS_ENABLED(CONFIG_FPU)) + return -EINVAL; + + return 0; +} + +static int riscv_ext_d_validate(const struct riscv_isa_ext_data *data, + const unsigned long *isa_bitmap) +{ + if (IS_ENABLED(CONFIG_FPU)) + return -EINVAL; + + return 0; +} + static int riscv_ext_vector_x_validate(const struct riscv_isa_ext_data *data, const unsigned long *isa_bitmap) { @@ -351,8 +374,8 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { __RISCV_ISA_EXT_DATA(i, RISCV_ISA_EXT_i), __RISCV_ISA_EXT_DATA(m, RISCV_ISA_EXT_m), __RISCV_ISA_EXT_DATA(a, RISCV_ISA_EXT_a), - __RISCV_ISA_EXT_DATA(f, RISCV_ISA_EXT_f), - __RISCV_ISA_EXT_DATA(d, RISCV_ISA_EXT_d), + __RISCV_ISA_EXT_DATA_VALIDATE(f, RISCV_ISA_EXT_f, riscv_ext_f_validate), + __RISCV_ISA_EXT_DATA_VALIDATE(d, RISCV_ISA_EXT_d, riscv_ext_d_validate), __RISCV_ISA_EXT_DATA(q, RISCV_ISA_EXT_q), __RISCV_ISA_EXT_SUPERSET(c, RISCV_ISA_EXT_c, riscv_c_exts), __RISCV_ISA_EXT_SUPERSET_VALIDATE(v, RISCV_ISA_EXT_v, riscv_v_exts, riscv_ext_vector_float_validate), @@ -912,15 +935,6 @@ void __init riscv_fill_hwcap(void) } } - /* - * We don't support systems with F but without D, so mask those out - * here. - */ - if ((elf_hwcap & COMPAT_HWCAP_ISA_F) && !(elf_hwcap & COMPAT_HWCAP_ISA_D)) { - pr_info("This kernel does not support systems with F but not D\n"); - elf_hwcap &= ~COMPAT_HWCAP_ISA_F; - } - if (__riscv_isa_extension_available(NULL, RISCV_ISA_EXT_ZVE32X)) { /* * This cannot fail when called on the boot hart