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AJvYcCWSNexRcwW749FmqlcGOgNyRtIifKoElEF0jcJbx/OkcIxzSsMoTl/gKsprsBUcuZfrFoh9mDfBYHZ9pw==@lists.infradead.org X-Gm-Message-State: AOJu0Ywk5vDY+N9w2eRrLhyfn5WGMNQLnUxYrk8s6zHRG2PZMsoSTPdP CSw6Kajia+5ekWJw6sSC8tO7aIIWwbuWYVHyW1NV405eq8kfE0WB X-Google-Smtp-Source: AGHT+IEPhKOYkZAH1L27GVScnktHV29Zg6rnYt7Aao9Pj+ivGpNBxOMvq6N+e5012LjWTi4Tl4hdpQ== X-Received: by 2002:a05:6a00:3c83:b0:717:8ee0:4ea1 with SMTP id d2e1a72fcca58-71de22e8399mr3349322b3a.0.1728029193671; Fri, 04 Oct 2024 01:06:33 -0700 (PDT) Received: from localhost ([2001:da8:7001:11::cb]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71de63d0014sm689798b3a.190.2024.10.04.01.06.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Oct 2024 01:06:33 -0700 (PDT) From: Inochi Amaoto To: Chen Wang , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Peter Zijlstra , Inochi Amaoto , Guo Ren , Lad Prabhakar , Hal Feng , Heikki Krogerus , Geert Uytterhoeven Cc: Yixun Lan , Inochi Amaoto , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH 1/3] dt-bindings: interrupt-controller: Add Sophgo SG2044 ACLINT SSWI Date: Fri, 4 Oct 2024 16:05:55 +0800 Message-ID: <20241004080557.2262872-2-inochiama@gmail.com> X-Mailer: git-send-email 2.46.2 In-Reply-To: <20241004080557.2262872-1-inochiama@gmail.com> References: <20241004080557.2262872-1-inochiama@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241004_010635_012458_87EFBBA2 X-CRM114-Status: GOOD ( 14.80 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Sophgo SG2044 has a new version of T-HEAD C920, which implement a fully featured ACLINT device. This ACLINT has an extra SSWI field to support fast S-mode IPI. Add necessary compatible string for the T-HEAD ACLINT sswi device. Signed-off-by: Inochi Amaoto --- .../thead,c900-aclint-sswi.yaml | 58 +++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-sswi.yaml -- 2.46.2 diff --git a/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-sswi.yaml b/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-sswi.yaml new file mode 100644 index 000000000000..0106fbf3ea1f --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-sswi.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/thead,c900-aclint-sswi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo sg2044 ACLINT Supervisor-level Software Interrupt Device + +maintainers: + - Inochi Amaoto + +description: + The SSWI device is a part of the riscv ACLINT device. It provides + supervisor-level IPI functionality for a set of HARTs on a RISC-V + platform. It provides a register to set an IPI (SETSSIP) for each + HART connected to the SSWI device. + +properties: + compatible: + items: + - enum: + - sophgo,sg2044-aclint-sswi + - const: thead,c900-aclint-sswi + + reg: + maxItems: 1 + + "#interrupt-cells": + const: 0 + + interrupt-controller: true + + interrupts-extended: + minItems: 1 + maxItems: 4095 + +additionalProperties: false + +required: + - compatible + - reg + - "#interrupt-cells" + - interrupt-controller + - interrupts-extended + +examples: + - | + interrupt-controller@94000000 { + compatible = "sophgo,sg2044-aclint-sswi", "thead,c900-aclint-sswi"; + reg = <0x94000000 0x00004000>; + #interrupt-cells = <0>; + interrupt-controller; + interrupts-extended = <&cpu1intc 1>, + <&cpu2intc 1>, + <&cpu3intc 1>, + <&cpu4intc 1>; + }; +...