From patchwork Fri Oct 11 14:00:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daire McNamara X-Patchwork-Id: 13832651 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EFBCED0D7BB for ; Fri, 11 Oct 2024 15:16:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Zt7JFQ4in+ER/UB831erRuuerXZB+7HL84Q8DVyPkYo=; b=4YV1TmI+bmg073 5Vd2R/BuWC/QPue1XYM3+lZWOhqzMLRBHiX5PJCw/2OkMpaCjLdg/2RrhkQkngDdEz0od25OKqXC9 1fA/NXFUBpClFqN+98nAB2K6rdTNuqxOfBk7Pu94Gpora0aXayRKNpXnRQY9knIm1EwGGYOTEtlKb V5DACtVt1w2tPoQMZ7QMaYqRLkGEXqTdP46u7d+9odoOdVcNFECIQzbl9Dy1tYxsVblF5PEnxq7Se jobNMX+IABCmrY6qLTlobqXz1Q3hNgl1stD8Q44UgYaJW9caGSogjh0Vvqmy1sfGyOrT0lNGym5/W KGetSbALJ90q4nVWwI/w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1szHNc-0000000GkZp-1gsl; Fri, 11 Oct 2024 15:16:36 +0000 Received: from esa.microchip.iphmx.com ([68.232.154.123]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1szGD5-0000000GXIw-1yiT for linux-riscv@lists.infradead.org; Fri, 11 Oct 2024 14:01:40 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1728655299; x=1760191299; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=dtxRXnBlCg/paGRmarwBeClVGbQZHAcN/95Mp8JrAzw=; b=TrBg7bx5PDnNaxtFHUlmOpmFUWVYPezKqrZan5XR9q2FkHd8HATMb1xs JoXAEMRYDtgI24cnug+zqWNJnFTuH1zZ41j8c9IyPU1cf8A0Eu8nfZTIl tPe68tkg2PAUgTXl7+Vmy+RPwjYBk8LNc7VUn8pzFRxm5Pf+jL7HpMvCN 3vkhMUm5Htt17F4V2cUZQ92UevguNCduX7k3nF6Xiaou1nuzZxUy68fZO ZyFH7WEVPzOyzNK7zVdLOihH8xrnxU9QNfBlE29g4GM7wekPIxmYZ+OL5 mMKBwUF3ugB99VrRJwS+cYUP6DoeCd5lbx96vfQnf5Gjl0KbrH6HQarZc Q==; X-CSE-ConnectionGUID: sEVvj1ptTw6T+pKPr7BM0w== X-CSE-MsgGUID: oB0LVEhBTS+CKBZj4qXJ+Q== X-IronPort-AV: E=Sophos;i="6.11,196,1725346800"; d="scan'208";a="33475205" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 11 Oct 2024 07:01:35 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Fri, 11 Oct 2024 07:01:31 -0700 Received: from wendy.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Fri, 11 Oct 2024 07:01:29 -0700 From: To: , CC: , , , , , , , , , , , Subject: [PATCH v10 1/3] PCI: microchip: Fix outbound address translation tables Date: Fri, 11 Oct 2024 15:00:41 +0100 Message-ID: <20241011140043.1250030-2-daire.mcnamara@microchip.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20241011140043.1250030-1-daire.mcnamara@microchip.com> References: <20241011140043.1250030-1-daire.mcnamara@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241011_070139_603570_F073F8EF X-CRM114-Status: GOOD ( 14.92 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Daire McNamara On Microchip PolarFire SoC (MPFS) the PCIe Root Port can be behind one of three general-purpose Fabric Interface Controller (FIC) buses that encapsulate an AXI-M interface. That FIC is responsible for managing the translations of the upper 32-bits of the AXI-M address. On MPFS, the Root Port driver needs to take account of that outbound address translation done by the parent FIC bus before setting up its own outbound address translation tables. In all cases on MPFS, the remaining outbound address translation tables are 32-bit only. Limit the outbound address translation tables to 32-bit only. Fixes: 6f15a9c9f941 ("PCI: microchip: Add Microchip Polarfire PCIe controller driver") Signed-off-by: Daire McNamara Acked-by: Conor Dooley Reviewed-by: Ilpo Jarvinen --- .../pci/controller/plda/pcie-microchip-host.c | 30 ++++++++++++++++--- 1 file changed, 26 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/plda/pcie-microchip-host.c b/drivers/pci/controller/plda/pcie-microchip-host.c index 48f60a04b740..fa4c85be21f0 100644 --- a/drivers/pci/controller/plda/pcie-microchip-host.c +++ b/drivers/pci/controller/plda/pcie-microchip-host.c @@ -21,6 +21,8 @@ #include "../../pci.h" #include "pcie-plda.h" +#define MC_OUTBOUND_TRANS_TBL_MASK GENMASK(31, 0) + /* PCIe Bridge Phy and Controller Phy offsets */ #define MC_PCIE1_BRIDGE_ADDR 0x00008000u #define MC_PCIE1_CTRL_ADDR 0x0000a000u @@ -612,6 +614,27 @@ static void mc_disable_interrupts(struct mc_pcie *port) writel_relaxed(GENMASK(31, 0), bridge_base_addr + ISTATUS_HOST); } +static int mc_pcie_setup_iomems(struct pci_host_bridge *bridge, + struct plda_pcie_rp *port) +{ + void __iomem *bridge_base_addr = port->bridge_addr; + struct resource_entry *entry; + u64 pci_addr; + u32 index = 1; + + resource_list_for_each_entry(entry, &bridge->windows) { + if (resource_type(entry->res) == IORESOURCE_MEM) { + pci_addr = entry->res->start - entry->offset; + plda_pcie_setup_window(bridge_base_addr, index, + entry->res->start & MC_OUTBOUND_TRANS_TBL_MASK, + pci_addr, resource_size(entry->res)); + index++; + } + } + + return 0; +} + static int mc_platform_init(struct pci_config_window *cfg) { struct device *dev = cfg->parent; @@ -622,15 +645,14 @@ static int mc_platform_init(struct pci_config_window *cfg) int ret; /* Configure address translation table 0 for PCIe config space */ - plda_pcie_setup_window(bridge_base_addr, 0, cfg->res.start, - cfg->res.start, - resource_size(&cfg->res)); + plda_pcie_setup_window(bridge_base_addr, 0, cfg->res.start & MC_OUTBOUND_TRANS_TBL_MASK, + 0, resource_size(&cfg->res)); /* Need some fixups in config space */ mc_pcie_enable_msi(port, cfg->win); /* Configure non-config space outbound ranges */ - ret = plda_pcie_setup_iomems(bridge, &port->plda); + ret = mc_pcie_setup_iomems(bridge, &port->plda); if (ret) return ret;