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Wed, 13 Nov 2024 18:21:41 -0800 (PST) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-211c7c499c9sm406875ad.68.2024.11.13.18.21.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Nov 2024 18:21:40 -0800 (PST) From: Charlie Jenkins Date: Wed, 13 Nov 2024 18:21:12 -0800 Subject: [PATCH v11 06/14] RISC-V: define the elements of the VCSR vector CSR MIME-Version: 1.0 Message-Id: <20241113-xtheadvector-v11-6-236c22791ef9@rivosinc.com> References: <20241113-xtheadvector-v11-0-236c22791ef9@rivosinc.com> In-Reply-To: <20241113-xtheadvector-v11-0-236c22791ef9@rivosinc.com> To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Jisheng Zhang , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Samuel Holland , Jonathan Corbet , Shuah Khan , Guo Ren , Evan Green , Jessica Clarke , Andrew Jones , Yangyu Chen , Andy Chiu Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Charlie Jenkins , Heiko Stuebner , Conor Dooley , Heiko Stuebner X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; 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X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Heiko Stuebner The VCSR CSR contains two elements VXRM[2:1] and VXSAT[0]. Define constants for those to access the elements in a readable way. Acked-by: Guo Ren Reviewed-by: Conor Dooley Signed-off-by: Heiko Stuebner Signed-off-by: Charlie Jenkins --- arch/riscv/include/asm/csr.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index fe5d4eb9adea..db1d26dfaef9 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -314,6 +314,10 @@ #define CSR_STIMECMP 0x14D #define CSR_STIMECMPH 0x15D +#define VCSR_VXRM_MASK 3 +#define VCSR_VXRM_SHIFT 1 +#define VCSR_VXSAT_MASK 1 + /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */ #define CSR_SISELECT 0x150 #define CSR_SIREG 0x151