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Wed, 13 Nov 2024 10:33:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=stgolabs.net; s=dreamhost; t=1731522812; bh=VulcaJeiOjCEiNlRQp/6xHIi1YJHEp/kfmwWLJnTfrA=; h=From:To:Cc:Subject:Date:Content-Transfer-Encoding; b=hSMTZP9EfFQPjhdjRj6vLQUeGBnkhgxb/U5yiuwU8vuxJUZFq8J3HYltaLascGphf BEi/KaMr84m1aB9mT2ktcjjq4/2ZYdenCvvNrlkNamEisztVtYqmui5sRWE/vBKa+o 3N1caEj2T7hBzQuHAt0CEYXUY+uobyZ52O+1TSRSYUhvaM8j/tnFxpxKvjnCFuXROc zbyqSEOEK0l7jyRCV5QDOQ3pC3zu/kAGXzDJmq43AiM15+8zel7Hz5KlSBROdQ0wCV hwJeGCHsk5sYROJQRdwWip59eUYfZqgwjZvsb/sBeqfwzDAEzQpA5NH9PNrG9/eCls pf35NWnAhd8pg== From: Davidlohr Bueso To: palmer@dabbelt.com Cc: jimw@sifive.com, guoren@kernel.org, dlustig@nvidia.com, parri.andrea@gmail.com, boqun.feng@gmail.com, peterz@infradead.org, will@kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, dave@stgolabs.net Subject: [PATCH] riscv/futex: Optimize atomic cmpxchg Date: Wed, 13 Nov 2024 10:33:21 -0800 Message-Id: <20241113183321.491113-1-dave@stgolabs.net> X-Mailer: git-send-email 2.39.5 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241113_103337_462670_7B05A61B X-CRM114-Status: UNSURE ( 6.39 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Remove redundant release/acquire barriers, optimizing the lr/sc sequence to provide conditional RCsc synchronization, per the RVWMO. Signed-off-by: Davidlohr Bueso Reviewed-by: Andrea Parri --- arch/riscv/include/asm/futex.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/futex.h b/arch/riscv/include/asm/futex.h index fc8130f995c1..72be100afa23 100644 --- a/arch/riscv/include/asm/futex.h +++ b/arch/riscv/include/asm/futex.h @@ -85,7 +85,7 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, __enable_user_access(); __asm__ __volatile__ ( - "1: lr.w.aqrl %[v],%[u] \n" + "1: lr.w %[v],%[u] \n" " bne %[v],%z[ov],3f \n" "2: sc.w.aqrl %[t],%z[nv],%[u] \n" " bnez %[t],1b \n"