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23 Dec 2024 12:56:15 +0000 (GMT) From: Michal Wilczynski To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, drew@pdp7.com, guoren@kernel.org, wefu@redhat.com, jassisinghbrar@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, frank.binns@imgtec.com, matt.coster@imgtec.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, ulf.hansson@linaro.org, jszhang@kernel.org, p.zabel@pengutronix.de, m.szyprowski@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org, Michal Wilczynski Subject: [RFC PATCH v2 12/19] dt-bindings: gpu: Add compatibles for T-HEAD TH1520 GPU Date: Mon, 23 Dec 2024 13:55:46 +0100 Message-Id: <20241223125553.3527812-13-m.wilczynski@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: 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CA CMS-TYPE: 201P X-CMS-RootMailID: 20241223125617eucas1p25256081c64ae4e64a12c6ec427f75e8e References: <20241223125553.3527812-1-m.wilczynski@samsung.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241223_045619_866953_898B3913 X-CRM114-Status: GOOD ( 12.21 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add a new SoC-specific compatible ("thead,th1520-gpu") for the T-HEAD TH1520 GPU, alongside the Imagination BXM family compatible ("img,img-bxm"). This documents the GPU integration on the T-HEAD platform. Also adjust clock name constraints to accommodate a second clock named "sys" instead of "mem" for T-HEAD. This is achieved by changing the order, and making the 'sys' appear before 'mem'. Provide example of the new GPU node. Signed-off-by: Michal Wilczynski --- .../bindings/gpu/img,powervr-rogue.yaml | 32 +++++++++++++++++-- 1 file changed, 30 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml index 4078cc816ea1..1eb1c15baec4 100644 --- a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml +++ b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml @@ -15,7 +15,10 @@ properties: items: - enum: - ti,am62-gpu - - const: img,img-axe # IMG AXE GPU model/revision is fully discoverable + - thead,th1520-gpu + - enum: + - img,img-axe # IMG AXE GPU model/revision is fully discoverable + - img,img-bxm reg: maxItems: 1 @@ -27,8 +30,8 @@ properties: clock-names: items: - const: core - - const: mem - const: sys + - const: mem minItems: 1 interrupts: @@ -62,6 +65,15 @@ allOf: properties: clocks: maxItems: 1 + - if: + properties: + compatible: + contains: + const: thead,th1520-gpu + then: + properties: + clocks: + maxItems: 2 examples: - | @@ -77,3 +89,19 @@ examples: interrupts = ; power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>; }; + + #include + #include + #include + + gpu: gpu@fff0000 { + compatible = "thead,th1520-gpu", "img,img-bxm"; + reg = <0xfff0000 0x1000>; + interrupt-parent = <&plic>; + interrupts = <102 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk CLK_GPU_CORE>, <&clk CLK_GPU_CFG_ACLK>; + clock-names = "core", "sys"; + power-domains = <&pd TH1520_AON_GPU_PD>; + resets = <&rst TH1520_RESET_ID_GPU>; + reset-names = "gpu"; + };