From patchwork Thu Jan 2 09:41:16 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Vladimir Kondratiev X-Patchwork-Id: 13924361 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5D75EE7718B for ; Thu, 2 Jan 2025 09:46:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=q/JX1acocSApomcApLdbH7thxutwZ0QUCMxuQj2FECA=; b=CrAgMOc5oI0c25 GR6Wz/nimVxbWF6XmDcpR7JxeKP083SFeI7o1zMlvq6lnHiTb0LkIphAmj7GksH7pfY/jnx3Cjtkl AavinL2sKpxmQ/ZUVrxi2zw21F0eaqwxRT1Zit4Vs1Tv4FsfdXKn0bPP/UWjP7BfU8XfktxGvNB/p N0C1wdOjXtKhzXZ/M69ZnfcPs9OUlf35/Q3B7Nu39YIozy3Cf7otguqV63Wytf1N2V4kp7EcfNSJl Ab0Tgaci6kB/tH4X3YAp/cjYW61laX055KrP55xgHPV1z2Y8kPboYvtFyf+jzsjLxxE0hobNtisjJ lkRGHJmpigUJY7kmkqiQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tTHlq-0000000A52K-28u7; Thu, 02 Jan 2025 09:45:38 +0000 Received: from esa3.hc555-34.eu.iphmx.com ([207.54.77.50]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tTHiE-0000000A4RQ-2c4R for linux-riscv@lists.infradead.org; Thu, 02 Jan 2025 09:41:58 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=mobileye.com; i=@mobileye.com; q=dns/txt; s=MoEyIP; t=1735810914; x=1767346914; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=4t8VRWBETfBHW77McqW8Ea3Z0LsArFzRtuIQqVimBZk=; b=QefntbNFoTMIVLmwm2L3V2iB0pdRSexSmt26g5YWZ5sOhrKJr+Zl6QHD FTkDPK9N5LFdotcVH8LlI8/fwBT43v2rtxuuqwjuNyEpLZJvpUcoHSD66 OoLHolGtk1LdQ76MvKH/OZMjTyiHJwZQYOklnPKAk1giw6xeqMgY/zTKr cBbJ0h59eTA0Rxrw+Ye2lyn3EOKltOzuqQc4Toi+cMJRHwO03ubkccpy+ Tu3mzqooD13uiEa9ARLzXDCeo7u4QIW3CaUa250SLBx/BD3D0JqXMKr17 m9dAz6ysm4zgZkqf9v0yH9zcj4oXoWBqAXlDWfXNL3BD+5CaU4E4OoV6j A==; X-CSE-ConnectionGUID: VQBwFtBaQ0CIO766q6Nz6A== X-CSE-MsgGUID: 9W6C6IK4SLShnJkhWAx6zQ== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from unknown (HELO ces02_data.me-corp.lan) ([146.255.191.134]) by esa3.hc555-34.eu.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jan 2025 11:41:48 +0200 X-CSE-ConnectionGUID: S5I1yFsdS8Ca0oSz2MxrJg== X-CSE-MsgGUID: QJ+VloP1QfSYRflZblHiRg== Received: from unknown (HELO epgd022.me-corp.lan) ([10.154.54.6]) by ces02_data.me-corp.lan with SMTP; 02 Jan 2025 11:41:46 +0200 Received: by epgd022.me-corp.lan (sSMTP sendmail emulation); Thu, 02 Jan 2025 11:41:47 +0200 From: Vladimir Kondratiev To: Anup Patel , Thomas Gleixner , Paul Walmsley , Palmer Dabbelt , Albert Ou , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Vladimir Kondratiev Subject: [PATCH 2/2] irqchip/riscv-aplic: add support for hart indexes Date: Thu, 2 Jan 2025 11:41:16 +0200 Message-ID: <20250102094116.3847894-3-vladimir.kondratiev@mobileye.com> In-Reply-To: <20250102094116.3847894-1-vladimir.kondratiev@mobileye.com> References: <20250102094116.3847894-1-vladimir.kondratiev@mobileye.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250102_014155_145731_4A72D017 X-CRM114-Status: GOOD ( 20.95 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Risc-V APLIC specification defines "hart index" in [1]: Within a given interrupt domain, each of the domain’s harts has a unique index number in the range 0 to 214 − 1 (= 16,383). The index number a domain associates with a hart may or may not have any relationship to the unique hart identifier (“hart ID”) that the RISC-V Privileged Architecture assigns to the hart. Two different interrupt domains may employ entirely different index numbers for the same set of harts. Support arbitrary hart indexes specified in optional APLIC property "riscv,hart-index" that should be array of u32 elements, one per interrupt target. If this property not specified, fallback is to use hart ids, with hart index for each APLIC to be (hartid - hartid0) where hartid0 is hart id for the 1-st target. [1]: https://github.com/riscv/riscv-aia Signed-off-by: Vladimir Kondratiev --- drivers/irqchip/irq-riscv-aplic-direct.c | 25 ++++++++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/irq-riscv-aplic-direct.c b/drivers/irqchip/irq-riscv-aplic-direct.c index 7cd6b646774b..80c82e34e894 100644 --- a/drivers/irqchip/irq-riscv-aplic-direct.c +++ b/drivers/irqchip/irq-riscv-aplic-direct.c @@ -221,12 +221,15 @@ static int aplic_direct_parse_parent_hwirq(struct device *dev, u32 index, int aplic_direct_setup(struct device *dev, void __iomem *regs) { + static const char *prop_hart_index = "riscv,hart-index"; int i, j, rc, cpu, current_cpu, setup_count = 0; struct aplic_direct *direct; struct irq_domain *domain; struct aplic_priv *priv; struct aplic_idc *idc; unsigned long hartid; + unsigned long hartid0; + u32 *hart_index = NULL; u32 v, hwirq; direct = devm_kzalloc(dev, sizeof(*direct), GFP_KERNEL); @@ -240,6 +243,22 @@ int aplic_direct_setup(struct device *dev, void __iomem *regs) return rc; } + rc = device_property_count_u32(dev, prop_hart_index); + if (rc == -ENODATA) + rc = 0; + if (rc > 0 && rc != priv->nr_idcs) + rc = -EOVERFLOW; + if (rc > 0) { + hart_index = devm_kcalloc(dev, priv->nr_idcs, sizeof(*hart_index), GFP_KERNEL); + if (!hart_index) + return -ENOMEM; + rc = device_property_read_u32_array(dev, prop_hart_index, + hart_index, priv->nr_idcs); + } + if (rc < 0) { + dev_err(dev, "APLIC property \"%s\" error %pe\n", prop_hart_index, ERR_PTR(rc)); + return rc; + } /* Setup per-CPU IDC and target CPU mask */ current_cpu = get_cpu(); for (i = 0; i < priv->nr_idcs; i++) { @@ -249,6 +268,8 @@ int aplic_direct_setup(struct device *dev, void __iomem *regs) continue; } + if (i == 0) + hartid0 = hartid; /* * Skip interrupts other than external interrupts for * current privilege level. @@ -265,8 +286,8 @@ int aplic_direct_setup(struct device *dev, void __iomem *regs) cpumask_set_cpu(cpu, &direct->lmask); idc = per_cpu_ptr(&aplic_idcs, cpu); - idc->hart_index = i; - idc->regs = priv->regs + APLIC_IDC_BASE + i * APLIC_IDC_SIZE; + idc->hart_index = hart_index ? hart_index[i] : hartid - hartid0; + idc->regs = priv->regs + APLIC_IDC_BASE + idc->hart_index * APLIC_IDC_SIZE; idc->direct = direct; aplic_idc_set_delivery(idc, true);