Message ID | 20250102204137.423081-2-e@freeshell.de (mailing list archive) |
---|---|
State | New |
Headers | show |
Series | riscv: dts: starfive: jh7110: More U-Boot downstream changes for JH7110 | expand |
On Thu, Jan 02, 2025 at 12:41:21PM -0800, E Shattow wrote: > no idea if this does anything useful; not needed for boot > > Signed-off-by: E Shattow <e@freeshell.de> > --- > arch/riscv/boot/dts/starfive/jh7110.dtsi | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi > index 0d8339357bad..0bc922b3ae8a 100644 > --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi > +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi > @@ -344,6 +344,15 @@ tdm_ext: tdm-ext-clock { > #clock-cells = <0>; > }; > > + timer { > + compatible = "riscv, timer"; compatible has an extra space, so won't do anything! > + interrupts-extended = <&cpu0_intc 5>, > + <&cpu1_intc 5>, > + <&cpu2_intc 5>, > + <&cpu3_intc 5>, > + <&cpu4_intc 5>; > + }; > + > soc { > compatible = "simple-bus"; > interrupt-parent = <&plic>; > -- > 2.45.2 >
On 1/13/25 10:39, Conor Dooley wrote: > On Thu, Jan 02, 2025 at 12:41:21PM -0800, E Shattow wrote: >> no idea if this does anything useful; not needed for boot >> >> Signed-off-by: E Shattow <e@freeshell.de> >> --- >> arch/riscv/boot/dts/starfive/jh7110.dtsi | 9 +++++++++ >> 1 file changed, 9 insertions(+) >> >> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi >> index 0d8339357bad..0bc922b3ae8a 100644 >> --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi >> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi >> @@ -344,6 +344,15 @@ tdm_ext: tdm-ext-clock { >> #clock-cells = <0>; >> }; >> >> + timer { >> + compatible = "riscv, timer"; > > compatible has an extra space, so won't do anything! > >> + interrupts-extended = <&cpu0_intc 5>, >> + <&cpu1_intc 5>, >> + <&cpu2_intc 5>, >> + <&cpu3_intc 5>, >> + <&cpu4_intc 5>; >> + }; >> + >> soc { >> compatible = "simple-bus"; >> interrupt-parent = <&plic>; >> -- >> 2.45.2 >> That extra space is my error and does not exist in U-Boot. Good catch! So, when corrected it appears to boot either way with or without and not any change in functionality that I can discern. My priority then for this series is to drop this patch as something unnecessary. Thanks, Conor! -E
On Fri, Jan 24, 2025 at 03:19:33AM -0800, E Shattow wrote: > > On 1/13/25 10:39, Conor Dooley wrote: > > On Thu, Jan 02, 2025 at 12:41:21PM -0800, E Shattow wrote: > > > no idea if this does anything useful; not needed for boot > > > > > > Signed-off-by: E Shattow <e@freeshell.de> > > > --- > > > arch/riscv/boot/dts/starfive/jh7110.dtsi | 9 +++++++++ > > > 1 file changed, 9 insertions(+) > > > > > > diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi > > > index 0d8339357bad..0bc922b3ae8a 100644 > > > --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi > > > +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi > > > @@ -344,6 +344,15 @@ tdm_ext: tdm-ext-clock { > > > #clock-cells = <0>; > > > }; > > > + timer { > > > + compatible = "riscv, timer"; > > > > compatible has an extra space, so won't do anything! > > > > > + interrupts-extended = <&cpu0_intc 5>, > > > + <&cpu1_intc 5>, > > > + <&cpu2_intc 5>, > > > + <&cpu3_intc 5>, > > > + <&cpu4_intc 5>; > > > + }; > > > + > > > soc { > > > compatible = "simple-bus"; > > > interrupt-parent = <&plic>; > > > -- > > > 2.45.2 > > > > > That extra space is my error and does not exist in U-Boot. Good catch! So, > when corrected it appears to boot either way with or without and not any > change in functionality that I can discern. My priority then for this series > is to drop this patch as something unnecessary. I don't mind having it, if it makes the hw description more complete, even if not used.
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index 0d8339357bad..0bc922b3ae8a 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -344,6 +344,15 @@ tdm_ext: tdm-ext-clock { #clock-cells = <0>; }; + timer { + compatible = "riscv, timer"; + interrupts-extended = <&cpu0_intc 5>, + <&cpu1_intc 5>, + <&cpu2_intc 5>, + <&cpu3_intc 5>, + <&cpu4_intc 5>; + }; + soc { compatible = "simple-bus"; interrupt-parent = <&plic>;
no idea if this does anything useful; not needed for boot Signed-off-by: E Shattow <e@freeshell.de> --- arch/riscv/boot/dts/starfive/jh7110.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+)