diff mbox series

rseq/selftests: Fix riscv rseq_offset_deref_addv inline asm

Message ID 20250103040326.2603734-1-shorne@gmail.com (mailing list archive)
State Superseded
Headers show
Series rseq/selftests: Fix riscv rseq_offset_deref_addv inline asm | expand

Checks

Context Check Description
conchuod/vmtest-for-next-PR success PR summary
conchuod/patch-1-test-1 success .github/scripts/patches/tests/build_rv32_defconfig.sh took 139.77s
conchuod/patch-1-test-2 success .github/scripts/patches/tests/build_rv64_clang_allmodconfig.sh took 1357.66s
conchuod/patch-1-test-3 success .github/scripts/patches/tests/build_rv64_gcc_allmodconfig.sh took 1583.76s
conchuod/patch-1-test-4 success .github/scripts/patches/tests/build_rv64_nommu_k210_defconfig.sh took 21.39s
conchuod/patch-1-test-5 success .github/scripts/patches/tests/build_rv64_nommu_virt_defconfig.sh took 23.04s
conchuod/patch-1-test-6 warning .github/scripts/patches/tests/checkpatch.sh took 0.68s
conchuod/patch-1-test-7 success .github/scripts/patches/tests/dtb_warn_rv64.sh took 43.87s
conchuod/patch-1-test-8 success .github/scripts/patches/tests/header_inline.sh took 0.01s
conchuod/patch-1-test-9 success .github/scripts/patches/tests/kdoc.sh took 0.55s
conchuod/patch-1-test-10 success .github/scripts/patches/tests/module_param.sh took 0.01s
conchuod/patch-1-test-11 success .github/scripts/patches/tests/verify_fixes.sh took 0.00s
conchuod/patch-1-test-12 success .github/scripts/patches/tests/verify_signedoff.sh took 0.03s

Commit Message

Stafford Horne Jan. 3, 2025, 4:03 a.m. UTC
When working on OpenRISC support for restartable sequences I noticed
and fixed these two issues with the riscv support bits.

 1 The 'inc' argument to RSEQ_ASM_OP_R_DEREF_ADDV was being implicitly
   passed to the macro.  Fix this by adding 'inc' to the list of macro
   arguments.
 2 The inline asm input constraints for 'inc' and 'off' use "er",  The
   riscv gcc port does not have an "e" constraint, this looks to be
   copied from the x86 port.  Fix this by just using an "r" constraint.

I have compile tested this only for riscv.  However, the same fixes I
use in the OpenRISC rseq selftests and everything passes with no issues.

Signed-off-by: Stafford Horne <shorne@gmail.com>
---
 tools/testing/selftests/rseq/rseq-riscv-bits.h | 6 +++---
 tools/testing/selftests/rseq/rseq-riscv.h      | 2 +-
 2 files changed, 4 insertions(+), 4 deletions(-)

Comments

Charlie Jenkins Jan. 10, 2025, 2:29 a.m. UTC | #1
On Fri, Jan 03, 2025 at 04:03:26AM +0000, Stafford Horne wrote:
> When working on OpenRISC support for restartable sequences I noticed
> and fixed these two issues with the riscv support bits.
> 
>  1 The 'inc' argument to RSEQ_ASM_OP_R_DEREF_ADDV was being implicitly
>    passed to the macro.  Fix this by adding 'inc' to the list of macro
>    arguments.
>  2 The inline asm input constraints for 'inc' and 'off' use "er",  The
>    riscv gcc port does not have an "e" constraint, this looks to be
>    copied from the x86 port.  Fix this by just using an "r" constraint.
> 
> I have compile tested this only for riscv.  However, the same fixes I
> use in the OpenRISC rseq selftests and everything passes with no issues.

Thank you for these changes! I suppose these tests hadn't been ran on
riscv before... I ran the tests on QEMU and they all passed :)

Tested-by: Charlie Jenkins <charlie@rivosinc.com>
Reviewed-by: Charlie Jenkins <charlie@rivosinc.com>

This should also have a fixes tag:

Fixes: 171586a6ab66 ("selftests/rseq: riscv: Template memory ordering and percpu access mode")

> 
> Signed-off-by: Stafford Horne <shorne@gmail.com>
> ---
>  tools/testing/selftests/rseq/rseq-riscv-bits.h | 6 +++---
>  tools/testing/selftests/rseq/rseq-riscv.h      | 2 +-
>  2 files changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/tools/testing/selftests/rseq/rseq-riscv-bits.h b/tools/testing/selftests/rseq/rseq-riscv-bits.h
> index de31a0143139..f02f411d550d 100644
> --- a/tools/testing/selftests/rseq/rseq-riscv-bits.h
> +++ b/tools/testing/selftests/rseq/rseq-riscv-bits.h
> @@ -243,7 +243,7 @@ int RSEQ_TEMPLATE_IDENTIFIER(rseq_offset_deref_addv)(intptr_t *ptr, off_t off, i
>  #ifdef RSEQ_COMPARE_TWICE
>  				  RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, "%l[error1]")
>  #endif
> -				  RSEQ_ASM_OP_R_DEREF_ADDV(ptr, off, 3)
> +				  RSEQ_ASM_OP_R_DEREF_ADDV(ptr, off, inc, 3)
>  				  RSEQ_INJECT_ASM(4)
>  				  RSEQ_ASM_DEFINE_ABORT(4, abort)
>  				  : /* gcc asm goto does not allow outputs */
> @@ -251,8 +251,8 @@ int RSEQ_TEMPLATE_IDENTIFIER(rseq_offset_deref_addv)(intptr_t *ptr, off_t off, i
>  				    [current_cpu_id]		"m" (rseq_get_abi()->RSEQ_TEMPLATE_CPU_ID_FIELD),
>  				    [rseq_cs]			"m" (rseq_get_abi()->rseq_cs.arch.ptr),
>  				    [ptr]			"r" (ptr),
> -				    [off]			"er" (off),
> -				    [inc]			"er" (inc)
> +				    [off]			"r" (off),
> +				    [inc]			"r" (inc)
>  				    RSEQ_INJECT_INPUT
>  				  : "memory", RSEQ_ASM_TMP_REG_1
>  				    RSEQ_INJECT_CLOBBER
> diff --git a/tools/testing/selftests/rseq/rseq-riscv.h b/tools/testing/selftests/rseq/rseq-riscv.h
> index 37e598d0a365..67d544aaa9a3 100644
> --- a/tools/testing/selftests/rseq/rseq-riscv.h
> +++ b/tools/testing/selftests/rseq/rseq-riscv.h
> @@ -158,7 +158,7 @@ do {									\
>  	"bnez	" RSEQ_ASM_TMP_REG_1 ", 222b\n"				\
>  	"333:\n"
>  
> -#define RSEQ_ASM_OP_R_DEREF_ADDV(ptr, off, post_commit_label)		\
> +#define RSEQ_ASM_OP_R_DEREF_ADDV(ptr, off, inc, post_commit_label)	\
>  	"mv	" RSEQ_ASM_TMP_REG_1 ", %[" __rseq_str(ptr) "]\n"	\
>  	RSEQ_ASM_OP_R_ADD(off)						\
>  	REG_L	  RSEQ_ASM_TMP_REG_1 ", 0(" RSEQ_ASM_TMP_REG_1 ")\n"	\
> -- 
> 2.47.0
> 
> 
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
Stafford Horne Jan. 10, 2025, 9:56 a.m. UTC | #2
On Thu, Jan 09, 2025 at 06:29:01PM -0800, Charlie Jenkins wrote:
> On Fri, Jan 03, 2025 at 04:03:26AM +0000, Stafford Horne wrote:
> > When working on OpenRISC support for restartable sequences I noticed
> > and fixed these two issues with the riscv support bits.
> > 
> >  1 The 'inc' argument to RSEQ_ASM_OP_R_DEREF_ADDV was being implicitly
> >    passed to the macro.  Fix this by adding 'inc' to the list of macro
> >    arguments.
> >  2 The inline asm input constraints for 'inc' and 'off' use "er",  The
> >    riscv gcc port does not have an "e" constraint, this looks to be
> >    copied from the x86 port.  Fix this by just using an "r" constraint.
> > 
> > I have compile tested this only for riscv.  However, the same fixes I
> > use in the OpenRISC rseq selftests and everything passes with no issues.
> 
> Thank you for these changes! I suppose these tests hadn't been ran on
> riscv before... I ran the tests on QEMU and they all passed :)

Thanks for confirming.

> Tested-by: Charlie Jenkins <charlie@rivosinc.com>
> Reviewed-by: Charlie Jenkins <charlie@rivosinc.com>
> 
> This should also have a fixes tag:
> 
> Fixes: 171586a6ab66 ("selftests/rseq: riscv: Template memory ordering and percpu access mode")

Right, If ok I think Palmer / the maintainer can add that when picking up the
patch.  If requested I can add that to a v2 though.

-Stafford

> > 
> > Signed-off-by: Stafford Horne <shorne@gmail.com>
> > ---
> >  tools/testing/selftests/rseq/rseq-riscv-bits.h | 6 +++---
> >  tools/testing/selftests/rseq/rseq-riscv.h      | 2 +-
> >  2 files changed, 4 insertions(+), 4 deletions(-)
> > 
> > diff --git a/tools/testing/selftests/rseq/rseq-riscv-bits.h b/tools/testing/selftests/rseq/rseq-riscv-bits.h
> > index de31a0143139..f02f411d550d 100644
> > --- a/tools/testing/selftests/rseq/rseq-riscv-bits.h
> > +++ b/tools/testing/selftests/rseq/rseq-riscv-bits.h
> > @@ -243,7 +243,7 @@ int RSEQ_TEMPLATE_IDENTIFIER(rseq_offset_deref_addv)(intptr_t *ptr, off_t off, i
> >  #ifdef RSEQ_COMPARE_TWICE
> >  				  RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, "%l[error1]")
> >  #endif
> > -				  RSEQ_ASM_OP_R_DEREF_ADDV(ptr, off, 3)
> > +				  RSEQ_ASM_OP_R_DEREF_ADDV(ptr, off, inc, 3)
> >  				  RSEQ_INJECT_ASM(4)
> >  				  RSEQ_ASM_DEFINE_ABORT(4, abort)
> >  				  : /* gcc asm goto does not allow outputs */
> > @@ -251,8 +251,8 @@ int RSEQ_TEMPLATE_IDENTIFIER(rseq_offset_deref_addv)(intptr_t *ptr, off_t off, i
> >  				    [current_cpu_id]		"m" (rseq_get_abi()->RSEQ_TEMPLATE_CPU_ID_FIELD),
> >  				    [rseq_cs]			"m" (rseq_get_abi()->rseq_cs.arch.ptr),
> >  				    [ptr]			"r" (ptr),
> > -				    [off]			"er" (off),
> > -				    [inc]			"er" (inc)
> > +				    [off]			"r" (off),
> > +				    [inc]			"r" (inc)
> >  				    RSEQ_INJECT_INPUT
> >  				  : "memory", RSEQ_ASM_TMP_REG_1
> >  				    RSEQ_INJECT_CLOBBER
> > diff --git a/tools/testing/selftests/rseq/rseq-riscv.h b/tools/testing/selftests/rseq/rseq-riscv.h
> > index 37e598d0a365..67d544aaa9a3 100644
> > --- a/tools/testing/selftests/rseq/rseq-riscv.h
> > +++ b/tools/testing/selftests/rseq/rseq-riscv.h
> > @@ -158,7 +158,7 @@ do {									\
> >  	"bnez	" RSEQ_ASM_TMP_REG_1 ", 222b\n"				\
> >  	"333:\n"
> >  
> > -#define RSEQ_ASM_OP_R_DEREF_ADDV(ptr, off, post_commit_label)		\
> > +#define RSEQ_ASM_OP_R_DEREF_ADDV(ptr, off, inc, post_commit_label)	\
> >  	"mv	" RSEQ_ASM_TMP_REG_1 ", %[" __rseq_str(ptr) "]\n"	\
> >  	RSEQ_ASM_OP_R_ADD(off)						\
> >  	REG_L	  RSEQ_ASM_TMP_REG_1 ", 0(" RSEQ_ASM_TMP_REG_1 ")\n"	\
> > -- 
> > 2.47.0
> > 
> > 
> > _______________________________________________
> > linux-riscv mailing list
> > linux-riscv@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-riscv
Mathieu Desnoyers Jan. 10, 2025, 4:22 p.m. UTC | #3
On 2025-01-02 23:03, Stafford Horne wrote:
> When working on OpenRISC support for restartable sequences I noticed
> and fixed these two issues with the riscv support bits.
> 
>   1 The 'inc' argument to RSEQ_ASM_OP_R_DEREF_ADDV was being implicitly
>     passed to the macro.  Fix this by adding 'inc' to the list of macro
>     arguments.
>   2 The inline asm input constraints for 'inc' and 'off' use "er",  The
>     riscv gcc port does not have an "e" constraint, this looks to be
>     copied from the x86 port.  Fix this by just using an "r" constraint.
> 
> I have compile tested this only for riscv.  However, the same fixes I
> use in the OpenRISC rseq selftests and everything passes with no issues.
> 
> Signed-off-by: Stafford Horne <shorne@gmail.com>

Reviewed-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>

> ---
>   tools/testing/selftests/rseq/rseq-riscv-bits.h | 6 +++---
>   tools/testing/selftests/rseq/rseq-riscv.h      | 2 +-
>   2 files changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/tools/testing/selftests/rseq/rseq-riscv-bits.h b/tools/testing/selftests/rseq/rseq-riscv-bits.h
> index de31a0143139..f02f411d550d 100644
> --- a/tools/testing/selftests/rseq/rseq-riscv-bits.h
> +++ b/tools/testing/selftests/rseq/rseq-riscv-bits.h
> @@ -243,7 +243,7 @@ int RSEQ_TEMPLATE_IDENTIFIER(rseq_offset_deref_addv)(intptr_t *ptr, off_t off, i
>   #ifdef RSEQ_COMPARE_TWICE
>   				  RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, "%l[error1]")
>   #endif
> -				  RSEQ_ASM_OP_R_DEREF_ADDV(ptr, off, 3)
> +				  RSEQ_ASM_OP_R_DEREF_ADDV(ptr, off, inc, 3)
>   				  RSEQ_INJECT_ASM(4)
>   				  RSEQ_ASM_DEFINE_ABORT(4, abort)
>   				  : /* gcc asm goto does not allow outputs */
> @@ -251,8 +251,8 @@ int RSEQ_TEMPLATE_IDENTIFIER(rseq_offset_deref_addv)(intptr_t *ptr, off_t off, i
>   				    [current_cpu_id]		"m" (rseq_get_abi()->RSEQ_TEMPLATE_CPU_ID_FIELD),
>   				    [rseq_cs]			"m" (rseq_get_abi()->rseq_cs.arch.ptr),
>   				    [ptr]			"r" (ptr),
> -				    [off]			"er" (off),
> -				    [inc]			"er" (inc)
> +				    [off]			"r" (off),
> +				    [inc]			"r" (inc)
>   				    RSEQ_INJECT_INPUT
>   				  : "memory", RSEQ_ASM_TMP_REG_1
>   				    RSEQ_INJECT_CLOBBER
> diff --git a/tools/testing/selftests/rseq/rseq-riscv.h b/tools/testing/selftests/rseq/rseq-riscv.h
> index 37e598d0a365..67d544aaa9a3 100644
> --- a/tools/testing/selftests/rseq/rseq-riscv.h
> +++ b/tools/testing/selftests/rseq/rseq-riscv.h
> @@ -158,7 +158,7 @@ do {									\
>   	"bnez	" RSEQ_ASM_TMP_REG_1 ", 222b\n"				\
>   	"333:\n"
>   
> -#define RSEQ_ASM_OP_R_DEREF_ADDV(ptr, off, post_commit_label)		\
> +#define RSEQ_ASM_OP_R_DEREF_ADDV(ptr, off, inc, post_commit_label)	\
>   	"mv	" RSEQ_ASM_TMP_REG_1 ", %[" __rseq_str(ptr) "]\n"	\
>   	RSEQ_ASM_OP_R_ADD(off)						\
>   	REG_L	  RSEQ_ASM_TMP_REG_1 ", 0(" RSEQ_ASM_TMP_REG_1 ")\n"	\
Shuah Khan Jan. 13, 2025, 10:59 p.m. UTC | #4
On 1/10/25 09:22, Mathieu Desnoyers wrote:
> On 2025-01-02 23:03, Stafford Horne wrote:
>> When working on OpenRISC support for restartable sequences I noticed
>> and fixed these two issues with the riscv support bits.
>>
>>   1 The 'inc' argument to RSEQ_ASM_OP_R_DEREF_ADDV was being implicitly
>>     passed to the macro.  Fix this by adding 'inc' to the list of macro
>>     arguments.
>>   2 The inline asm input constraints for 'inc' and 'off' use "er",  The
>>     riscv gcc port does not have an "e" constraint, this looks to be
>>     copied from the x86 port.  Fix this by just using an "r" constraint.
>>
>> I have compile tested this only for riscv.  However, the same fixes I
>> use in the OpenRISC rseq selftests and everything passes with no issues.
>>
>> Signed-off-by: Stafford Horne <shorne@gmail.com>
> 
> Reviewed-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
> 

If these are going through risc repo

Acked-by: Shuah Khan <skhan@linuxfoundation.org>

If you would like me to take this, let me know.

thanks,
-- Shuah
Stafford Horne Jan. 14, 2025, 5:04 p.m. UTC | #5
On Mon, Jan 13, 2025 at 03:59:24PM -0700, Shuah Khan wrote:
> On 1/10/25 09:22, Mathieu Desnoyers wrote:
> > On 2025-01-02 23:03, Stafford Horne wrote:
> > > When working on OpenRISC support for restartable sequences I noticed
> > > and fixed these two issues with the riscv support bits.
> > > 
> > >   1 The 'inc' argument to RSEQ_ASM_OP_R_DEREF_ADDV was being implicitly
> > >     passed to the macro.  Fix this by adding 'inc' to the list of macro
> > >     arguments.
> > >   2 The inline asm input constraints for 'inc' and 'off' use "er",  The
> > >     riscv gcc port does not have an "e" constraint, this looks to be
> > >     copied from the x86 port.  Fix this by just using an "r" constraint.
> > > 
> > > I have compile tested this only for riscv.  However, the same fixes I
> > > use in the OpenRISC rseq selftests and everything passes with no issues.
> > > 
> > > Signed-off-by: Stafford Horne <shorne@gmail.com>
> > 
> > Reviewed-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
> > 
> 
> If these are going through risc repo
> 
> Acked-by: Shuah Khan <skhan@linuxfoundation.org>
> 
> If you would like me to take this, let me know.

Thanks, I have not heard from Palmer yet regarding what he wants to do.  I will
send a v2 aggregating the Reviewed-by/Acked-by hopefully that will help.

-Stafford
diff mbox series

Patch

diff --git a/tools/testing/selftests/rseq/rseq-riscv-bits.h b/tools/testing/selftests/rseq/rseq-riscv-bits.h
index de31a0143139..f02f411d550d 100644
--- a/tools/testing/selftests/rseq/rseq-riscv-bits.h
+++ b/tools/testing/selftests/rseq/rseq-riscv-bits.h
@@ -243,7 +243,7 @@  int RSEQ_TEMPLATE_IDENTIFIER(rseq_offset_deref_addv)(intptr_t *ptr, off_t off, i
 #ifdef RSEQ_COMPARE_TWICE
 				  RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, "%l[error1]")
 #endif
-				  RSEQ_ASM_OP_R_DEREF_ADDV(ptr, off, 3)
+				  RSEQ_ASM_OP_R_DEREF_ADDV(ptr, off, inc, 3)
 				  RSEQ_INJECT_ASM(4)
 				  RSEQ_ASM_DEFINE_ABORT(4, abort)
 				  : /* gcc asm goto does not allow outputs */
@@ -251,8 +251,8 @@  int RSEQ_TEMPLATE_IDENTIFIER(rseq_offset_deref_addv)(intptr_t *ptr, off_t off, i
 				    [current_cpu_id]		"m" (rseq_get_abi()->RSEQ_TEMPLATE_CPU_ID_FIELD),
 				    [rseq_cs]			"m" (rseq_get_abi()->rseq_cs.arch.ptr),
 				    [ptr]			"r" (ptr),
-				    [off]			"er" (off),
-				    [inc]			"er" (inc)
+				    [off]			"r" (off),
+				    [inc]			"r" (inc)
 				    RSEQ_INJECT_INPUT
 				  : "memory", RSEQ_ASM_TMP_REG_1
 				    RSEQ_INJECT_CLOBBER
diff --git a/tools/testing/selftests/rseq/rseq-riscv.h b/tools/testing/selftests/rseq/rseq-riscv.h
index 37e598d0a365..67d544aaa9a3 100644
--- a/tools/testing/selftests/rseq/rseq-riscv.h
+++ b/tools/testing/selftests/rseq/rseq-riscv.h
@@ -158,7 +158,7 @@  do {									\
 	"bnez	" RSEQ_ASM_TMP_REG_1 ", 222b\n"				\
 	"333:\n"
 
-#define RSEQ_ASM_OP_R_DEREF_ADDV(ptr, off, post_commit_label)		\
+#define RSEQ_ASM_OP_R_DEREF_ADDV(ptr, off, inc, post_commit_label)	\
 	"mv	" RSEQ_ASM_TMP_REG_1 ", %[" __rseq_str(ptr) "]\n"	\
 	RSEQ_ASM_OP_R_ADD(off)						\
 	REG_L	  RSEQ_ASM_TMP_REG_1 ", 0(" RSEQ_ASM_TMP_REG_1 ")\n"	\