Message ID | 20250109113814.3254448-2-vladimir.kondratiev@mobileye.com (mailing list archive) |
---|---|
State | Superseded |
Headers | show |
Series | riscv,aplic: support for hart indexes | expand |
On Thu, Jan 09, 2025 at 01:38:13PM +0200, Vladimir Kondratiev wrote: > Document optional property "riscv,hart-indexes" > > Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> > Reviewed-by: Anup Patel <anup@brainfault.org> > --- > .../bindings/interrupt-controller/riscv,aplic.yaml | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml > index 190a6499c932..bef00521d5da 100644 > --- a/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml > +++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml > @@ -91,6 +91,14 @@ properties: > Firmware must configure interrupt delegation registers based on > interrupt delegation list. > > + riscv,hart-indexes: > + $ref: /schemas/types.yaml#/definitions/uint32-array > + minItems: 1 > + maxItems: 16384 > + description: > + A list of hart indexes that APLIC should use to address each hart > + that is mentioned in the "interrupts-extended" Wouldn't using the 'cpus' property linking to each cpu/hart node work? Rob
On Thu, Jan 09, 2025 at 01:38:13PM +0200, Vladimir Kondratiev wrote: > Document optional property "riscv,hart-indexes" That is obvious reading the diff. Why do you need this? Also, what happens when this property is not present? > > Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> > Reviewed-by: Anup Patel <anup@brainfault.org> > --- > .../bindings/interrupt-controller/riscv,aplic.yaml | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml > index 190a6499c932..bef00521d5da 100644 > --- a/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml > +++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml > @@ -91,6 +91,14 @@ properties: > Firmware must configure interrupt delegation registers based on > interrupt delegation list. > > + riscv,hart-indexes: > + $ref: /schemas/types.yaml#/definitions/uint32-array > + minItems: 1 > + maxItems: 16384 > + description: > + A list of hart indexes that APLIC should use to address each hart > + that is mentioned in the "interrupts-extended" > + > dependencies: > riscv,delegation: [ "riscv,children" ] > > -- > 2.43.0 >
>Wouldn't using the 'cpus' property linking to each cpu/hart node work? >Rob Hi, unfortunately, per-CPU property would not work. "hart index" defined per interrupt domain, and different controllers may define it differently. This is from the "4.3 Hart index numbers" section of the interrupts spec found at https://github.com/riscv/riscv-aia Within a given interrupt domain, each of the domain’s harts has a unique index number in the range 0 to 2^14 − 1 (= 16,383).
>> Document optional property "riscv,hart-indexes" >That is obvious reading the diff. Why do you need this? I say it briefly in the description for the property. In more details this is described in the other patch comment - for code that uses this property. Is it better to repeat more detailed description in this patch comment as well? >Also, what happens when this property is not present? Logical hart index get used, i.e. index in the "extended-interrupts" Shall I add full explanation to this patch comment? This one, it is a comment from the 2-nd patch in this set: Risc-V APLIC specification defines "hart index" in [1]: Within a given interrupt domain, each of the domain’s harts has a unique index number in the range 0 to 2^14 − 1 (= 16,383). The index number a domain associates with a hart may or may not have any relationship to the unique hart identifier (“hart ID”) that the RISC-V Privileged Architecture assigns to the hart. Two different interrupt domains may employ entirely different index numbers for the same set of harts. Further, this document says in "4.5 Memory-mapped control region for an interrupt domain": The array of IDC structures may include some for potential hart index numbers that are not actual hart index numbers in the domain. For example, the first IDC structure is always for hart index 0, but 0 is not necessarily a valid index number for any hart in the domain. Support arbitrary hart indexes specified in optional APLIC property "riscv,hart-indexes" that should be array of u32 elements, one per interrupt target. If this property not specified, fallback is to use logical hart indexes within the domain. [1]: https://github.com/riscv/riscv-aia Thanks, Vladimir
On Sun, Jan 12 2025 at 08:38, Vladimir Kondratiev wrote: >>> Document optional property "riscv,hart-indexes" > >>That is obvious reading the diff. Why do you need this? > > I say it briefly in the description for the property. > In more details this is described in the other patch comment > - for code that uses this property. > Is it better to repeat more detailed description in this patch > comment as well? Obviously. Each patch has to be self contained and explain what it is about. Thanks, tglx
diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml index 190a6499c932..bef00521d5da 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml @@ -91,6 +91,14 @@ properties: Firmware must configure interrupt delegation registers based on interrupt delegation list. + riscv,hart-indexes: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 16384 + description: + A list of hart indexes that APLIC should use to address each hart + that is mentioned in the "interrupts-extended" + dependencies: riscv,delegation: [ "riscv,children" ]